MC33390 - DP256 BDLC problem
combo? I'm using a standard J1850 simulator/monitor to test my system
and can successfully send/receive frames so I assume my BDLC driver is
constructed properly (based on HC08 code in Moto doc AN1731). What has
me baffled are the hw hacks I've had to use to make things work.
My hw design is mostly consistant with the MC33390 doc (no MOV between
the 470pf cap and the bus - Vbat comes directly from my 12V regulated
supply) but will only work if I put pullup resistors on the
BDLC/tranceiver tx-rx lines and a pull down on the bus line. When the
BDLC is enabled the bus idles at 1V and when the BDLC is disabled it
idles at 5.5V. I don't think this is kosher but it works. This
arrangement was derived after noticing that J1850 comms worked while the
CAN tranceiver traces to CAN0 were in place but not after being
severed. Since the MC33390 is non-inverting I cannot understand why I
need the pull ups (PERM and PPSM registers are not changed from reset
Can anyone offer me advise (I'm a sw guy - not a J1850 phy layer expert)?