I am running the Metrowerks Code Warrior xgate command line compiler and
assembler in Eclipse.
I've got the following issues:
1) The following instruction won't assemble with axgate.exe: TFR R6,PC
Gives: ERROR A22005: Number or type of operands mismatch.
Compiler listing gives 06fa, which is TFR R6, PC, according to the
Freescale xgate manual.
As far as I can tell, this is the correct format for the instruction.
Am I missing something ?
2) Compiler generates an instruction of STW R6,(-SP) and gives a
machine code of
7E1E
Format should be: STW R6,(RX,-SP) where RX is a register.
7E1E yields STW R6,(R0,-R7)... so SP must be R7 in their setup. R0 must
be implied ?
Shouldn't the R0 register be specified in the instruction text ?
3) Compiler generates an instruction of LDW R6,(SP+) with a machine code
of
6e1d.
Format should be: LDW R6,(RX,-SP) where RX is a register.
6e1d yields LDW R6,(R0,R7+).. so again R7 must be SP and R0 is the base,
which makes sense.
The two compiler errors are for pushing and pulling subroutine
calls. The machine code it emits is correct, but the assembler list is
wrong. Unless R0 is implied when an operand is missing. Is the
assembler supposed to know that if an operand is missing it means it is
R0 ?
Here is the version information:
axgate.exe -v
Assembler for XGATE V-5.0.3 Build 5051, Feb 25 2005
cxgate.exe -v
ANSI-C/cC++ Compiler for XGATE V-5.0.3 Build 5051, Feb 25 2005
I installed the service pack that was included with my 9S12XDP512 kit.
--
Kim Lux, Diesel Research Inc.
Bugs or feature in Code Warrior Xgate stuff ?
Started by ●November 22, 2005
Reply by ●November 22, 20052005-11-22
Kim Lux wrote:
>I am running the Metrowerks Code Warrior xgate command line compiler and
>assembler in Eclipse. Interesting. I intent to try to setup this, but I did not find the time yet.
>I've got the following issues: >1) The following instruction won't assemble with axgate.exe: TFR R6,PC
>
>Gives: ERROR A22005: Number or type of operands mismatch.
>
>Compiler listing gives 06fa, which is TFR R6, PC, according to the
>Freescale xgate manual.
>
>As far as I can tell, this is the correct format for the instruction.
>
>Am I missing something ? No, the assembler misses something. The first silicon of the XGATE did
not have the "TFR R?,PC" instruction. It looks like the assembler did
not learn it in time.
I will make sure this is fixed in the next release.
>
>2) Compiler generates an instruction of STW R6,(-SP) and gives a
>machine code of
>7E1E
>
>Format should be: STW R6,(RX,-SP) where RX is a register.
>
>7E1E yields STW R6,(R0,-R7)... so SP must be R7 in their setup. R0 must
>be implied ?
>
>Shouldn't the R0 register be specified in the instruction text ? >
>3) Compiler generates an instruction of LDW R6,(SP+) with a machine code
>of
>6e1d.
>
>Format should be: LDW R6,(RX,-SP) where RX is a register.
>
>6e1d yields LDW R6,(R0,R7+).. so again R7 must be SP and R0 is the base,
>which makes sense.
>
>The two compiler errors are for pushing and pulling subroutine
>calls. The machine code it emits is correct, but the assembler list is
>wrong. Unless R0 is implied when an operand is missing. Is the
>assembler supposed to know that if an operand is missing it means it is
>R0 ? As you noticed, the compiler did really mean such an implicit "R0".
However, the compiler listing file is
not used by any assembler, it is for humans only. The compiler does
directly generate object files without the
use of the assembler. This also explains why the compiler does support
the "TFR R?,PC" while the assembler lacks support for it.
>Here is the version information:
>
>axgate.exe -v
>Assembler for XGATE V-5.0.3 Build 5051, Feb 25 2005
>
>cxgate.exe -v
>ANSI-C/cC++ Compiler for XGATE V-5.0.3 Build 5051, Feb 25 2005
>
>I installed the service pack that was included with my 9S12XDP512 kit. >
Daniel
>I am running the Metrowerks Code Warrior xgate command line compiler and
>assembler in Eclipse. Interesting. I intent to try to setup this, but I did not find the time yet.
>I've got the following issues: >1) The following instruction won't assemble with axgate.exe: TFR R6,PC
>
>Gives: ERROR A22005: Number or type of operands mismatch.
>
>Compiler listing gives 06fa, which is TFR R6, PC, according to the
>Freescale xgate manual.
>
>As far as I can tell, this is the correct format for the instruction.
>
>Am I missing something ? No, the assembler misses something. The first silicon of the XGATE did
not have the "TFR R?,PC" instruction. It looks like the assembler did
not learn it in time.
I will make sure this is fixed in the next release.
>
>2) Compiler generates an instruction of STW R6,(-SP) and gives a
>machine code of
>7E1E
>
>Format should be: STW R6,(RX,-SP) where RX is a register.
>
>7E1E yields STW R6,(R0,-R7)... so SP must be R7 in their setup. R0 must
>be implied ?
>
>Shouldn't the R0 register be specified in the instruction text ? >
>3) Compiler generates an instruction of LDW R6,(SP+) with a machine code
>of
>6e1d.
>
>Format should be: LDW R6,(RX,-SP) where RX is a register.
>
>6e1d yields LDW R6,(R0,R7+).. so again R7 must be SP and R0 is the base,
>which makes sense.
>
>The two compiler errors are for pushing and pulling subroutine
>calls. The machine code it emits is correct, but the assembler list is
>wrong. Unless R0 is implied when an operand is missing. Is the
>assembler supposed to know that if an operand is missing it means it is
>R0 ? As you noticed, the compiler did really mean such an implicit "R0".
However, the compiler listing file is
not used by any assembler, it is for humans only. The compiler does
directly generate object files without the
use of the assembler. This also explains why the compiler does support
the "TFR R?,PC" while the assembler lacks support for it.
>Here is the version information:
>
>axgate.exe -v
>Assembler for XGATE V-5.0.3 Build 5051, Feb 25 2005
>
>cxgate.exe -v
>ANSI-C/cC++ Compiler for XGATE V-5.0.3 Build 5051, Feb 25 2005
>
>I installed the service pack that was included with my 9S12XDP512 kit. >
Daniel
Reply by ●November 22, 20052005-11-22
On Tue, 2005-11-22 at 11:33 +0100, Daniel Friederich wrote:
> Kim Lux wrote:
>
> >I am running the Metrowerks Code Warrior xgate command line compiler and
> >assembler in Eclipse.
> >
> >
> Interesting. I intent to try to setup this, but I did not find the time yet.
Eclipse is an outstanding IDE IMHO. It runs on most platforms, it has a
ton of built in tools, one can add their own tools, it works for
multiple languages, etc. I highly recommend it.
> >I've got the following issues:
> >
> >
> >1) The following instruction won't assemble with axgate.exe: TFR R6,PC
> >
> >Gives: ERROR A22005: Number or type of operands mismatch.
> >
> >Compiler listing gives 06fa, which is TFR R6, PC, according to the
> >Freescale xgate manual.
> >
> >As far as I can tell, this is the correct format for the instruction.
> >
> >Am I missing something ?
> >
> No, the assembler misses something. The first silicon of the XGATE did
> not have the "TFR R?,PC" instruction. It looks like the assembler did
> not learn it in time.
> I will make sure this is fixed in the next release.
When exactly will that be ?
> >
> >2) Compiler generates an instruction of STW R6,(-SP) and gives a
> >machine code of
> >7E1E
> >
> >Format should be: STW R6,(RX,-SP) where RX is a register.
> >
> >7E1E yields STW R6,(R0,-R7)... so SP must be R7 in their setup. R0 must
> >be implied ?
> >
> >Shouldn't the R0 register be specified in the instruction text ?
> >
> >
> >
> >3) Compiler generates an instruction of LDW R6,(SP+) with a machine code
> >of
> >6e1d.
> >
> >Format should be: LDW R6,(RX,-SP) where RX is a register.
> >
> >6e1d yields LDW R6,(R0,R7+).. so again R7 must be SP and R0 is the base,
> >which makes sense.
> >
> >The two compiler errors are for pushing and pulling subroutine
> >calls. The machine code it emits is correct, but the assembler list is
> >wrong. Unless R0 is implied when an operand is missing. Is the
> >assembler supposed to know that if an operand is missing it means it is
> >R0 ?
> >
> As you noticed, the compiler did really mean such an implicit "R0".
> However, the compiler listing file is
> not used by any assembler, it is for humans only.
I like to compile to assembly code and then assemble into machine code.
This allows me to do some fixup/changes between the compiler and
assembler. This also means that the assembly language output isn't just
for humans as far as I am concerned.
While you are at it, could you have the compiler output proper function
headers in assembly as well as structs, variables, etc. That sort of
stuff seems to have been left out of the listing.
> The compiler does
> directly generate object files without the
> use of the assembler. This also explains why the compiler does support
> the "TFR R?,PC" while the assembler lacks support for it.
Like I said, I'd like a 2 step process.
I get the eerie feeling that I am one of the early adopters (testers) of
the whole 9S12X EVB kit.
--
Kim Lux, Diesel Research Inc.
> Kim Lux wrote:
>
> >I am running the Metrowerks Code Warrior xgate command line compiler and
> >assembler in Eclipse.
> >
> >
> Interesting. I intent to try to setup this, but I did not find the time yet.
Eclipse is an outstanding IDE IMHO. It runs on most platforms, it has a
ton of built in tools, one can add their own tools, it works for
multiple languages, etc. I highly recommend it.
> >I've got the following issues:
> >
> >
> >1) The following instruction won't assemble with axgate.exe: TFR R6,PC
> >
> >Gives: ERROR A22005: Number or type of operands mismatch.
> >
> >Compiler listing gives 06fa, which is TFR R6, PC, according to the
> >Freescale xgate manual.
> >
> >As far as I can tell, this is the correct format for the instruction.
> >
> >Am I missing something ?
> >
> No, the assembler misses something. The first silicon of the XGATE did
> not have the "TFR R?,PC" instruction. It looks like the assembler did
> not learn it in time.
> I will make sure this is fixed in the next release.
When exactly will that be ?
> >
> >2) Compiler generates an instruction of STW R6,(-SP) and gives a
> >machine code of
> >7E1E
> >
> >Format should be: STW R6,(RX,-SP) where RX is a register.
> >
> >7E1E yields STW R6,(R0,-R7)... so SP must be R7 in their setup. R0 must
> >be implied ?
> >
> >Shouldn't the R0 register be specified in the instruction text ?
> >
> >
> >
> >3) Compiler generates an instruction of LDW R6,(SP+) with a machine code
> >of
> >6e1d.
> >
> >Format should be: LDW R6,(RX,-SP) where RX is a register.
> >
> >6e1d yields LDW R6,(R0,R7+).. so again R7 must be SP and R0 is the base,
> >which makes sense.
> >
> >The two compiler errors are for pushing and pulling subroutine
> >calls. The machine code it emits is correct, but the assembler list is
> >wrong. Unless R0 is implied when an operand is missing. Is the
> >assembler supposed to know that if an operand is missing it means it is
> >R0 ?
> >
> As you noticed, the compiler did really mean such an implicit "R0".
> However, the compiler listing file is
> not used by any assembler, it is for humans only.
I like to compile to assembly code and then assemble into machine code.
This allows me to do some fixup/changes between the compiler and
assembler. This also means that the assembly language output isn't just
for humans as far as I am concerned.
While you are at it, could you have the compiler output proper function
headers in assembly as well as structs, variables, etc. That sort of
stuff seems to have been left out of the listing.
> The compiler does
> directly generate object files without the
> use of the assembler. This also explains why the compiler does support
> the "TFR R?,PC" while the assembler lacks support for it.
Like I said, I'd like a 2 step process.
I get the eerie feeling that I am one of the early adopters (testers) of
the whole 9S12X EVB kit.
--
Kim Lux, Diesel Research Inc.
Reply by ●November 22, 20052005-11-22
--- In 68HC12@68HC..., Kim Lux <lux@d...> wrote:
> I get the eerie feeling that I am one of the early adopters
> (testers) of
> the whole 9S12X EVB kit.
>
> --
> Kim Lux, Diesel Research Inc.
>
Uh, could that be because 9S12X just came out, and nobody except
Freescale has been able to get ahold of a chip?
> I get the eerie feeling that I am one of the early adopters
> (testers) of
> the whole 9S12X EVB kit.
>
> --
> Kim Lux, Diesel Research Inc.
>
Uh, could that be because 9S12X just came out, and nobody except
Freescale has been able to get ahold of a chip?
