PLL - how to tie signals if not used

Started by blewis999 February 4, 2006
I seem to remember in the doc set or an appnote somewhere that if the 
pll was not being used, one of the signals should be tied (to Vcc ? or 
gnd?). But I can't find where this was. We have a need to disable the 
pll because of an error in the pcb layout and need to remove the 
components, can someone suggest the best practise please. Thanks in 
advance

Robert Lewis
	
Robert,

The official Freescale recommendation is to connect the Xfc pin to VDDPLL 
if the internal PLL is not used.

Hope this helps,
Doron
Nohau
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html

At 18:20 03/02/2006 -0800, you wrote:
>I seem to remember in the doc set or an appnote somewhere that if the
>pll was not being used, one of the signals should be tied (to Vcc ? or
>gnd?). But I can't find where this was. We have a need to disable the
>pll because of an error in the pcb layout and need to remove the
>components, can someone suggest the best practise please. Thanks in
>advance
>
>Robert Lewis
	
	
What if you don't plan to use the PLL today but want to keep the option
open
for the future? What is the risk of connecting the PLL but not enabling it?

-Dan

-----Original Message-----
From: 68HC12@68HC... [mailto:68HC12@68HC...]On Behalf Of
Doron Fael
Sent: Sunday, February 05, 2006 2:04 AM
To: 68HC12@68HC...
Subject: Re: [68HC12] PLL - how to tie signals if not used
	Robert,

The official Freescale recommendation is to connect the Xfc pin to VDDPLL
if the internal PLL is not used.

Hope this helps,
Doron
Nohau
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html

At 18:20 03/02/2006 -0800, you wrote:
>I seem to remember in the doc set or an appnote somewhere that if the
>pll was not being used, one of the signals should be tied (to Vcc ? or
>gnd?). But I can't find where this was. We have a need to disable the
>pll because of an error in the pcb layout and need to remove the
>components, can someone suggest the best practise please. Thanks in
>advance
>
>Robert Lewis
	
	Yahoo! Groups Links
	
Daniel White wrote:

> What if you don't plan to use the PLL today but
want to keep the option open
> for the future? What is the risk of connecting the PLL but not enabling it?

IMHO no problem. The CPU will always start without PLL. I can't 
imagine think that leakeage curents will pull the pin to illegal 
levels, and the external filter components prevent from excessive 
noise.

Oliver
-- 
Oliver Betz, Muenchen
	
Dan,

In that case, just make sure to include the network of two capacitors and a 
resistors on your board, connected to the Xfc pin. This way,if and when you 
will want to use the internal PLL in the future you will be able to do so. 
Until then, you may simply keep the PLL de-selected, so your device will 
always work at half the Crystal speed.

Hope this helps,
Doron
Nohau
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html

At 19:44 06/02/2006 -0500, you wrote:
>What if you don't plan to use the PLL today but want to keep the option open
>for the future? What is the risk of connecting the PLL but not enabling it?
>
>-Dan
>
>-----Original Message-----
>From: 68HC12@68HC... [mailto:68HC12@68HC...]On Behalf Of
>Doron Fael
>Sent: Sunday, February 05, 2006 2:04 AM
>To: 68HC12@68HC...
>Subject: Re: [68HC12] PLL - how to tie signals if not used
>
>
>Robert,
>
>The official Freescale recommendation is to connect the Xfc pin to VDDPLL
>if the internal PLL is not used.
>
>Hope this helps,
>Doron
>Nohau
>HC12 In-Circuit Emulators
>www.nohau.com/emul12pc.html
>
>At 18:20 03/02/2006 -0800, you wrote:
> >I seem to remember in the doc set or an appnote somewhere that if the
> >pll was not being used, one of the signals should be tied (to Vcc ? or
> >gnd?). But I can't find where this was. We have a need to disable the
> >pll because of an error in the pcb layout and need to remove the
> >components, can someone suggest the best practise please. Thanks in
> >advance
> >
> >Robert Lewis