HCS12D PLL Woes

Started by Jonathan Masters January 17, 2008
Hi all,

I am just upgrading a product and will for only the second time use the
PLL. In the first instance, the clock was only multiplied up from 8MHz
to 12.5MHz and I haven't experienced any problems with that product.

In the current instance the bus clock is being multiplied up from 8MHz
to 25MHz. Now I have all sorts of problems with the (PEMICRO) BDM pods.
(Yes I have set CLKSW and am aware of the BDM bug).

The debugger will show the program stopping on a BKGD instruction at a
location not in flash. The location is (nearly) always the same.
Sometimes however the system gets up and goes normally - then dies only
when I attempt to write to EEPROM.

My questions are two:

i) How sensitive are the component values for the XFC filter. The values
I am using don't match the Filter Calculator values - simply because I
am trying lots of different REFDV/SYNR values and can't be bothered
changing the components if it isn't necessary.

ii) Is it just one of those things that BDM is unreliable at these clock
speeds? The pods are my experience very noise sensitive and I wouldn't
be surprised if they don't go at higher specs. Does anyone regularly use
PE pods in this type of setup?

Any other suggestions would be appreciated - the wheels are turning but
the bus isn't going anywhere :(
This isn't going to help but as an aside I've never been able to debug
with the pll in operation. If I need to do source level debugging
(techarts bdm with noice12) I compile with a conditional preprocessor
define that switches the pll off. This define is also used to condition
the timing for other subsystems (ie: sci baudrate). If anyone knows a
work-around I'd be grateful for their insight.

-rob

On Thu, January 17, 2008 12:57 am, Jonathan Masters wrote:
> Hi all,
> I am just upgrading a product and will for only the second time use the
> PLL. In the first instance, the clock was only multiplied up from 8MHz
> to 12.5MHz and I haven't experienced any problems with that product.
>
> In the current instance the bus clock is being multiplied up from 8MHz
> to 25MHz. Now I have all sorts of problems with the (PEMICRO) BDM pods.
> (Yes I have set CLKSW and am aware of the BDM bug).
> The debugger will show the program stopping on a BKGD instruction at a
> location not in flash. The location is (nearly) always the same. Sometimes
> however the system gets up and goes normally - then dies only when I
> attempt to write to EEPROM.
>
> My questions are two:
> i) How sensitive are the component values for the XFC filter. The values I
> am using don't match the Filter Calculator values - simply because I am
> trying lots of different REFDV/SYNR values and can't be bothered changing
> the components if it isn't necessary.
>
> ii) Is it just one of those things that BDM is unreliable at these clock
> speeds? The pods are my experience very noise sensitive and I wouldn't be
> surprised if they don't go at higher specs. Does anyone regularly use PE
> pods in this type of setup?
>
> Any other suggestions would be appreciated - the wheels are turning but
> the bus isn't going anywhere :(
>
Hi All,
I have successfully use the PLL while debugging with the PE-USB
Multilink Interface(BDM). The PLL can only be set up in multiple
of the base clock. For 8Mh cyrstal, the PLL can be set up for 48MHz,
which yelds an 24M Hz MCU clock. Freescale has an program that will
calculate the CAPS, RESISTOR and Settings for the PLL.
Bruce

--- In 6..., robmilne@... wrote:
>
> This isn't going to help but as an aside I've never been able to
debug
> with the pll in operation. If I need to do source level debugging
> (techarts bdm with noice12) I compile with a conditional
preprocessor
> define that switches the pll off. This define is also used to
condition
> the timing for other subsystems (ie: sci baudrate). If anyone
knows a
> work-around I'd be grateful for their insight.
>
> -rob
>
> On Thu, January 17, 2008 12:57 am, Jonathan Masters wrote:
> > Hi all,
> >
> >
> > I am just upgrading a product and will for only the second time
use the
> > PLL. In the first instance, the clock was only multiplied up from
8MHz
> > to 12.5MHz and I haven't experienced any problems with that
product.
> >
> > In the current instance the bus clock is being multiplied up from
8MHz
> > to 25MHz. Now I have all sorts of problems with the (PEMICRO) BDM
pods.
> > (Yes I have set CLKSW and am aware of the BDM bug).
> >
> >
> > The debugger will show the program stopping on a BKGD instruction
at a
> > location not in flash. The location is (nearly) always the same.
Sometimes
> > however the system gets up and goes normally - then dies only
when I
> > attempt to write to EEPROM.
> >
> > My questions are two:
> >
> >
> > i) How sensitive are the component values for the XFC filter. The
values I
> > am using don't match the Filter Calculator values - simply
because I am
> > trying lots of different REFDV/SYNR values and can't be bothered
changing
> > the components if it isn't necessary.
> >
> > ii) Is it just one of those things that BDM is unreliable at
these clock
> > speeds? The pods are my experience very noise sensitive and I
wouldn't be
> > surprised if they don't go at higher specs. Does anyone regularly
use PE
> > pods in this type of setup?
> >
> > Any other suggestions would be appreciated - the wheels are
turning but
> > the bus isn't going anywhere :(
>
For what it is worth I *always* run the clock at 48Mhz from an 8Mhz
clock with P&E and I have never had a problem.
Hello,

I posted the PLL Filter calculator at the following location:
http://forums.freescale.com/freescale/board/message?board.idBITCOMM&message.id80

By using the divider of the PLL, you can have a base clock of 1 MHz
and therefore multiply by 15 if you wish.
I precise this because I thought in the post you were indicating that
the crystal was the base clock. However you can any frequency from it.
not only mutliples of 8 MHz.

Cheers,
Alban Rampon.
http://www.k-noo.net/
--- In 6..., "bruceembry" wrote:
>
> Hi All,
> I have successfully use the PLL while debugging with the PE-USB
> Multilink Interface(BDM). The PLL can only be set up in multiple
> of the base clock. For 8Mh cyrstal, the PLL can be set up for 48MHz,
> which yelds an 24M Hz MCU clock. Freescale has an program that will
> calculate the CAPS, RESISTOR and Settings for the PLL.
> Bruce
>
> --- In 6..., robmilne@ wrote:
> >
> > This isn't going to help but as an aside I've never been able to
> debug
> > with the pll in operation. If I need to do source level debugging
> > (techarts bdm with noice12) I compile with a conditional
> preprocessor
> > define that switches the pll off. This define is also used to
> condition
> > the timing for other subsystems (ie: sci baudrate). If anyone
> knows a
> > work-around I'd be grateful for their insight.
> >
> > -rob
> >
> > On Thu, January 17, 2008 12:57 am, Jonathan Masters wrote:
> > > Hi all,
> > >
> > >
> > > I am just upgrading a product and will for only the second time
> use the
> > > PLL. In the first instance, the clock was only multiplied up from
> 8MHz
> > > to 12.5MHz and I haven't experienced any problems with that
> product.
> > >
> > > In the current instance the bus clock is being multiplied up from
> 8MHz
> > > to 25MHz. Now I have all sorts of problems with the (PEMICRO) BDM
> pods.
> > > (Yes I have set CLKSW and am aware of the BDM bug).
> > >
> > >
> > > The debugger will show the program stopping on a BKGD instruction
> at a
> > > location not in flash. The location is (nearly) always the same.
> Sometimes
> > > however the system gets up and goes normally - then dies only
> when I
> > > attempt to write to EEPROM.
> > >
> > > My questions are two:
> > >
> > >
> > > i) How sensitive are the component values for the XFC filter. The
> values I
> > > am using don't match the Filter Calculator values - simply
> because I am
> > > trying lots of different REFDV/SYNR values and can't be bothered
> changing
> > > the components if it isn't necessary.
> > >
> > > ii) Is it just one of those things that BDM is unreliable at
> these clock
> > > speeds? The pods are my experience very noise sensitive and I
> wouldn't be
> > > surprised if they don't go at higher specs. Does anyone regularly
> use PE
> > > pods in this type of setup?
> > >
> > > Any other suggestions would be appreciated - the wheels are
> turning but
> > > the bus isn't going anywhere :(
> > >
>