trouble in BDM debugger when PLL gets ON- HC12

Started by imtiyazfmn October 21, 2011
Hello,
I am using BDM debugger for my 9S12d64 device normally it works fine but when i am going to switch internal clock to PLL clock it gets halt and gets disconnected so please give your suggestions for this.
Thanks,
Imtiyaz

Check the errata for your chip, and the settings in your debugger

Does the issue affect ONLY the debugger? That
is, does your program continue to run, or does it die as well?

The errata for the MC9S12D64 includes
MUCts00818: PLL If osc_clock is 2 to 3
times pll_clock, STOP can cause SCM or reset.

Don't know if that would cover your situation.
The MC9S12DP256 (popular on eval boards) and some
others have a bug related to PLL and BDM. Quoting NoICE's help
Unfortunately, some types of HCS12 (including the
A, Dx, and H) contain a bug, described in
Motorola/Freescale errata, that causes BDM to
stop working when the PLL is enabled and BDM is
operating in the default mode. For such chips, it
is necessary to set the CLKSW bit in the BDM
status register at startup. Then, when the PLL is
enabled and the processor speed changes, NoICE
must change the BDM speed to match.
NoICE and most other debuggers have work-arounds,
but you may need to enable them manually (NoICE
builds it into its target ini file)

The errata for the MC9S12D64 doesn't list this
bug, but perhaps your debugger is incorrectly
expecting this behavior and you need to disable it.
At 10:07 AM 10/21/2011, imtiyazfmn wrote:
>Hello,
>I am using BDM debugger for my 9S12d64 device
>normally it works fine but when i am going to
>switch internal clock to PLL clock it gets halt
>and gets disconnected so please give your suggestions for this.
>Thanks,
>Imtiyaz

Best regards, John Hartman
NoICE Debugging Tools
http://www.noicedebugger.com