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HCS12 Nested Timer Interrupts

Started by varneybob January 3, 2003
I am using the HCS12 eval board and have a mask set 1K79X part.
While executing the Timer5 interrupt service routine, I need to be
interrupted by a higher-priority Timer4 interrupt service routine.
However, it appears that the higher-priority Timer4 interrupt is
never gaining access to the MCU.

Through the debugger, I see that the TFLG register shows both the
Timer4 and Timer5 flags are set (thus if the corresponding TIE bits
are set, then an interrupt should be generated). And, the
corresponding TIE bits are indeed set, however I do not receive an
interrupt for Timer4 - I remain waiting in the Timer5 ISR.

I've got a few things I want to look at (like if the I bit in the CCR
is set or not), but does anyone else have any suggestions?

Thanks.



It turns out the I bit did get set so I had to first clear the TFLG
bit associated with Timer5, then do a CLI, and everything turned out
okay.

Now however, I'm experiencing a very odd problem where it appears
that an interrupt gets fired and throws my code into the weeds....

I'll post more as I learn more... --- In , "varneybob <varneybob@y...>"
<varneybob@y...> wrote:
> I am using the HCS12 eval board and have a mask set 1K79X part.
> While executing the Timer5 interrupt service routine, I need to be
> interrupted by a higher-priority Timer4 interrupt service routine.
> However, it appears that the higher-priority Timer4 interrupt is
> never gaining access to the MCU.
>
> Through the debugger, I see that the TFLG register shows both the
> Timer4 and Timer5 flags are set (thus if the corresponding TIE bits
> are set, then an interrupt should be generated). And, the
> corresponding TIE bits are indeed set, however I do not receive an
> interrupt for Timer4 - I remain waiting in the Timer5 ISR.
>
> I've got a few things I want to look at (like if the I bit in the
CCR
> is set or not), but does anyone else have any suggestions?
>
> Thanks.




>but does anyone else have any suggestions?
Re-enable interrupt inside ISR4?


In a message dated 1/3/03 10:14:54 AM Eastern Standard Time,
writes:

> Now however, I'm experiencing a very odd problem where it appears
> that an interrupt gets fired and throws my code into the weeds....
>

I recall an errata that says something about an I interrupt happening during
an rti will cause a vector to 0xffc0 (way before the key wakeup vectors). So
put a handler there and flash a led if you service it... then rti....