# Maximum SPI bus speed

Started by January 22, 2003
 p 83 of the MC(S12A256 Device Guide V01.00 states that the maximum value of the Spi bus is 1/4 of the bus frequency. Page 17 of the SPI Block Users Guide V02.06 states that the maximum frequency can be Bus clock /2. Which is correct?
 Is this due to the distinction between transmit speed and receive speed? Typically the receive speed is 2X the transmit speed. 607-656-2597 -----Original Message----- From: [mailto:] Sent: Wednesday, January 22, 2003 2:58 PM To: Cc: Subject: [68HC12] Maximum SPI bus speed p 83 of the MC(S12A256 Device Guide V01.00 states that the maximum value of the Spi bus is 1/4 of the bus frequency. Page 17 of the SPI Block Users Guide V02.06 states that the maximum frequency can be Bus clock /2. Which is correct? -------------------- ">http://docs.yahoo.com/info/terms/
 The SPI bus acting as a master sends and receives data at the same time and only has one clock so I am confused about your statement. Kellogg Dave <> 01/22/2003 05:22 PM Please respond to 68HC12 To: "'" <> cc: Subject: RE: [68HC12] Maximum SPI bus speed Is this due to the distinction between transmit speed and receive speed? Typically the receive speed is 2X the transmit speed. 607-656-2597 -----Original Message----- From: [mailto:] Sent: Wednesday, January 22, 2003 2:58 PM To: Cc: Subject: [68HC12] Maximum SPI bus speed p 83 of the MC(S12A256 Device Guide V01.00 states that the maximum value of the Spi bus is 1/4 of the bus frequency. Page 17 of the SPI Block Users Guide V02.06 states that the maximum frequency can be Bus clock /2. Which is correct? -------------------- ">http://docs.yahoo.com/info/terms/ -------------------- ">http://docs.yahoo.com/info/terms/
 I should have been clearer. The master is the device sourcing the clock. In some cases, the slave mode is spec'ed at 2x the frequency of the master mode. I imagine that this is to guarantee that the slave can keep up with a master without marginal conditions. However, I may be wrong here. I referenced the Electrical Characteristics - MC9S12DP256 V0.3 (which is probably old), and see that the max for both Master and slave operating frequency is 1/4 e-clock. There are several timing diagrams in the Electrical Characteristics for the SPI that may help explain the timing. 607-656-2597 -----Original Message----- From: [mailto:] Sent: Thursday, January 23, 2003 7:35 AM To: Subject: RE: [68HC12] Maximum SPI bus speed The SPI bus acting as a master sends and receives data at the same time and only has one clock so I am confused about your statement. Kellogg Dave <> 01/22/2003 05:22 PM Please respond to 68HC12 To: "'" <> cc: Subject: RE: [68HC12] Maximum SPI bus speed Is this due to the distinction between transmit speed and receive speed? Typically the receive speed is 2X the transmit speed. 607-656-2597 -----Original Message----- From: [mailto:] Sent: Wednesday, January 22, 2003 2:58 PM To: Cc: Subject: [68HC12] Maximum SPI bus speed p 83 of the MC(S12A256 Device Guide V01.00 states that the maximum value of the Spi bus is 1/4 of the bus frequency. Page 17 of the SPI Block Users Guide V02.06 states that the maximum frequency can be Bus clock /2. Which is correct? -------------------- ">http://docs.yahoo.com/info/terms/ -------------------- ">http://docs.yahoo.com/info/terms/ -------------------- ">http://docs.yahoo.com/info/terms/
 Rod: Take a look at page 17 of http://e-www.motorola.com/brdata/PDFDB/docs/S12SPIV2.pdf. The fastest SPI speed is 1/2 of the bus clock. Also, the speed of the transmit and receive are the same. This must be done since the shift register shifts one bit in as it shifts one bit out. Regards, John Honnold Motorola SPS Technical Information Center MCU 16/32 Bit Applications Engineer ********************************** This Email has been classified: ( ) Motorola Internal Use Only ( ) Motorola Confidential Proprietary ( ) For Your Eyes Only (x) Public -----Original Message----- From: [mailto:] Sent: Wednesday, January 22, 2003 12:58 PM To: Amos Olubunmi Cc: Subject: [68HC12] Maximum SPI bus speed p 83 of the MC(S12A256 Device Guide V01.00 states that the maximum value of the Spi bus is 1/4 of the bus frequency. Page 17 of the SPI Block Users Guide V02.06 states that the maximum frequency can be Bus clock /2. Which is correct? -------------------- ">http://docs.yahoo.com/info/terms/
 I received this from our local Motorola rep: The max SPI rate for master mode operation is 1/2 ECLK. The max SPI rate for slave mode operation is 1/4 ECLK. This is not what the A256 documentation states though! We are replacing an HC11 application with a HC12 and if we were restricted to 1/4 ECLK for the master we would need to bump up the Oscillator and consume more power. RN Kellogg Dave <> 01/23/2003 09:37 AM Please respond to 68HC12 To: "'" <> cc: Subject: RE: [68HC12] Maximum SPI bus speed I should have been clearer. The master is the device sourcing the clock. In some cases, the slave mode is spec'ed at 2x the frequency of the master mode. I imagine that this is to guarantee that the slave can keep up with a master without marginal conditions. However, I may be wrong here. I referenced the Electrical Characteristics - MC9S12DP256 V0.3 (which is probably old), and see that the max for both Master and slave operating frequency is 1/4 e-clock. There are several timing diagrams in the Electrical Characteristics for the SPI that may help explain the timing. 607-656-2597 -----Original Message----- From: [mailto:] Sent: Thursday, January 23, 2003 7:35 AM To: Subject: RE: [68HC12] Maximum SPI bus speed The SPI bus acting as a master sends and receives data at the same time and only has one clock so I am confused about your statement. Kellogg Dave <> 01/22/2003 05:22 PM Please respond to 68HC12 To: "'" <> cc: Subject: RE: [68HC12] Maximum SPI bus speed Is this due to the distinction between transmit speed and receive speed? Typically the receive speed is 2X the transmit speed. 607-656-2597 -----Original Message----- From: [mailto:] Sent: Wednesday, January 22, 2003 2:58 PM To: Cc: Subject: [68HC12] Maximum SPI bus speed p 83 of the MC(S12A256 Device Guide V01.00 states that the maximum value of the Spi bus is 1/4 of the bus frequency. Page 17 of the SPI Block Users Guide V02.06 states that the maximum frequency can be Bus clock /2. Which is correct? -------------------- ">http://docs.yahoo.com/info/terms/ -------------------- ">http://docs.yahoo.com/info/terms/ -------------------- ">http://docs.yahoo.com/info/terms/ -------------------- ">http://docs.yahoo.com/info/terms/