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(I believe mask 1K79X is the latest version.) This bug's worth some advertising I think... Quote from errata sheet: SCI INTERRUPT ASSERTS ONLY IF AN ODD NUMBER OF INTERRUPTS ACTIVE MUCTS00510 The interrupt of the SCI is only asserted if an odd number of interrupts is active (i.e. flags set and enabled). Example: If an Transmit data register empty and an receive ready interrupt are active at the same time the interrupt request to the CPU is not asserted. This can lead to missing interrupts or spurious interrupts i.e. the request gets deasserted before the CPU fetches the interrupt vector. Those spurious interrutps will execute on the SWI vector. The interrupt flag setting is always correct. |
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'S12DP256 - errata for all 0K79X and 1K79X masks
Started by ●July 12, 2002
Reply by ●July 29, 20022002-07-29
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WOW! The word "defective" comes to mind. This would be completely
unusable application. Paul > -----Original Message----- > From: bruce_at_pocket_neurobics > [mailto:] > Sent: Friday, July 12, 2002 4:36 AM > To: > Subject: [68HC12] 'S12DP256 - errata for all 0K79X and 1K79X masks > (I believe mask 1K79X is the latest version.) > > This bug's worth some advertising I think... > Quote from errata sheet: > > SCI INTERRUPT ASSERTS ONLY IF AN ODD NUMBER OF INTERRUPTS ACTIVE > MUCTS00510 > The interrupt of the SCI is only asserted if an odd number of > interrupts is active (i.e. flags set and enabled). Example: If an > Transmit data register empty and an receive ready interrupt are active > at the same time the interrupt request to the CPU is not asserted. > This can lead to missing interrupts or spurious interrupts i.e. the > request gets deasserted before the CPU fetches the interrupt vector. > Those spurious > interrutps will execute on the SWI vector. The interrupt flag setting > is always correct. > > > -------------------- > > ">http://docs.yahoo.com/info/terms/ > |
