Three component PLL network useless?

Started by Oliver Betz July 13, 2002
Hi All,

anybody out there with some knowledge of the D60(A) PLL behaviour?

I think the three component (R+C)||C network is not better than a
single capacitor. Maybe even worse!

It would be great to read some other opinion on this topic.

I compared a (10nF+5,6kOhm)||1nF against a single 10nF capacitor.
8MHz XTAL, 8MHz bus frequency, REFDV=1, SYNR=1 (same results with
REFDV=0, SYNR=0).

I switched off the PLL, discharged the capacitor(s), switched on the
PLL and observed PLLCR:ACQ and PLLFLG:LOCK as well as the XFC voltage
(with a high impedance probe).

The time in "acquisistion mode" is not much less with the three
component network. No wonder, since there is no more current to
charge the capacitors (33uA in my case). The voltage at XFC is a
linear ramp in both cases with similar slope.

But there is a big disadvantage using the resistor: the PLL switches
to tracking mode too early because there is 33uA*5,6kOhms0mV drop
over the resistor. Then, in tracking mode, there is only little
current to charge the capacitor by this remaining voltage.

I measured 300us acq. + 300us tracking until locked with the 3
component network. With a single capacitor it was 320us acq. + 100us
tracking until locked.

As far as I see, the 3 component network locks slower, costs more and
is less reliable. Is there any advantage I overlooked? Or did
Motorola overlook something?

Motorola support says "The 3 component design is used allow a
combination of fast ramping and minimizing overshoot." But I don't
believe this:

- On the one hand I see no overshoot with a single capacitor. So
there is nothing to improve.

- On the other hand it doesn't take into account the change from
acquisistion mode to tracking mode making the overall response worse
than with a single capacitor.

I hope there are still readers on this list with some "analog"
knowledge to discuss this topic.

Oliver




Oliver,

I don't have any experience with the D60, nor the HC12, however I am
digging thru the docs on the '9S12DP256 for an app where the PLL will be
very important. Your earlier post was intriguing. (Maybe the following
covers what you already know...)

The single capacitor filter provides an RC (the R is inside the chip) loop
filter, i.e. a transfer function of the form 1/(s*t+1), where "t" is the RC
time constant. This filter function makes a 2nd order PLL loop which is
(should be!) unconditionally stable. The reason the simple filter is not
commonly used is that it limits the parameters that can be varied to meet
loop specifications (Gardner, _Phaselock Techniques_, Wiley, 1966, has a
nice exposition in the second chapter). The loop gain is also fixed (i.e.
the maximum gain is fixed, and like R, unspecified). This means that for a
given loop damping factor the loop cutoff freq is fixed; usually, both of
these are specified, so an additional parameter that can be set is required.

With a series R, and parallel leg of a series RC, (the Mot network without
1 nf cap) there are two time constants, which gives more freedom to set the
loop parameters. The 1 nf parallel cap improves filtering for the high
freqs coming out of the phase detector, and being 10x smaller than the loop
determining cap is not a large factor in the loop dynamics. Excluding this
cap in the analysis makes the analysis much easier, i.e. 2nd order is
easily, whereas including makes it a 3rd order loop. McDermott, _Wireless
Digital Communications Design and Theory_, TAPR, 1996, shows some curves
for an example of one resistor, two cap filter (the Mot network including
the 1 nf), and points out that 2nd cap (the 1 nf) helps the high freq
rolloff of the loop.

Your measurements indicate that the single 10nf cap must be "good enough."
If the cap is increased (t becomes larger), then the damping factor should
decrease (linearly) and the cutoff freq decrease (by square root). If the
dividers are set to something other than unity they figure into the cutoff
and damping (the data sheet for the MC145170-2 PLL has the equations).
Consequently, the single cap scheme might not work so well if the
synthesizer register divides by, say, 10. That would increase the damping
factor by 10 and reduce the cutoff freq by sqrt(10). Gardner shows an
approximation for time-to-lock that varies by the 4th power of the cutoff
freq, i.e. the time would increase by 100.

For the single cap scheme you should be able to put in different size caps
and see the difference. As the cap increases, at some point, I would
expect to see overshoot on the XFC pin (but the time-to-lock might become
too large). (If I had the hardware setup I do some experimenting.)

Another factor is the noise bandwidth, hence jitter, is minimum when the
damping is about 0.5, but the penalty for being overdamped is not large. I
suspect for these reasons Mot recommends the 1 resistor, 2 cap network.
The problem is that they do not publish the gain (Kvco * Kphasedetector),
nor an equivalent source resistance, so one is left doing some
experimenting. AN2219 says that the using the ideas in the AN should not
be a substitute for measurement.

Overall, it looks the one cap scheme ought to be quite satisfactory for
many situations.

The pullin/lock seems to be the critical factor in for a MCU, i.e. getting
sufficient stability before coming out of reset. I noticed that the
startup counter has been increased from 4096 in the 912DG128 to 8192 in the
'9S12. Furthermore, the '9S12 also includes a high/low bandwidth filter
for acquisition/tracking (this is an item that could use something more
specific that "narrow" and "wide"!).

It would nice if Mot would publish some typical parameters for the PLL so
one wasn't faced with doing "black box" experimenting. Regards,

Donald E Haselwood

PS: I noticed they changed the terminology in the Star from, "Limp Home
Mode" to "Self Clocked Mode"--I really like the LHM term; catches ones
attention. IMO, SCM is just another computer jargon term. At 11:31 AM 7/13/02 +0200, you wrote:
>Hi All,
>
>anybody out there with some knowledge of the D60(A) PLL behaviour?
>
>I think the three component (R+C)||C network is not better than a
>single capacitor. Maybe even worse!
>
>It would be great to read some other opinion on this topic.
>
>I compared a (10nF+5,6kOhm)||1nF against a single 10nF capacitor.
>8MHz XTAL, 8MHz bus frequency, REFDV=1, SYNR=1 (same results with
>REFDV=0, SYNR=0).
>
>I switched off the PLL, discharged the capacitor(s), switched on the
>PLL and observed PLLCR:ACQ and PLLFLG:LOCK as well as the XFC voltage
>(with a high impedance probe).
>
>The time in "acquisistion mode" is not much less with the three
>component network. No wonder, since there is no more current to
>charge the capacitors (33uA in my case). The voltage at XFC is a
>linear ramp in both cases with similar slope.
>
>But there is a big disadvantage using the resistor: the PLL switches
>to tracking mode too early because there is 33uA*5,6kOhms0mV drop
>over the resistor. Then, in tracking mode, there is only little
>current to charge the capacitor by this remaining voltage.
>
>I measured 300us acq. + 300us tracking until locked with the 3
>component network. With a single capacitor it was 320us acq. + 100us
>tracking until locked.
>
>As far as I see, the 3 component network locks slower, costs more and
>is less reliable. Is there any advantage I overlooked? Or did
>Motorola overlook something?
>
>Motorola support says "The 3 component design is used allow a
>combination of fast ramping and minimizing overshoot." But I don't
>believe this:
>
>- On the one hand I see no overshoot with a single capacitor. So
>there is nothing to improve.
>
>- On the other hand it doesn't take into account the change from
>acquisistion mode to tracking mode making the overall response worse
>than with a single capacitor.
>
>I hope there are still readers on this list with some "analog"
>knowledge to discuss this topic.
>
>Oliver >-------------------- >
>">http://docs.yahoo.com/info/terms/ >




Donald E Haselwood <> wrote:

>I don't have any experience with the D60, nor the HC12, however I am
>digging thru the docs on the '9S12DP256 for an app where the PLL will be

AFAIS there is no noticeable functional difference other than the
wider VCO range. The most important difference is that the HCS12 has
better documentation.

>very important. Your earlier post was intriguing. (Maybe the following

What means "very imporant": do you need to *change* the bus frequency
(VCO) rapidly? Tight jitter requirements? Leaky boards? Or do you
simply want a fast start of the PLL?

>covers what you already know...)
>
>The single capacitor filter provides an RC (the R is inside the chip) loop

To my knowledge there is a current source, and the current seems to be
proportional to the phase difference. No "R inside the chip".

I assume that the current source is controlled by some latched XOR
function so that large frequency differences result in continuous
current. That's what I can read from the docs and observe by looking
at XFC with a scope.

BTW: when switching off the PLL for a short period can result in 180
degree phase error which results in little output current. In this
case it can take very long (e.g. 1ms) until the PLL locks again.

The VCO input is the voltage at XFC so this is a nice solution to have
the phase comparator output and the VCO input at one bidirectional
pin.

The external R makes a P component (intended for faster response)
while the series C makes a I component (to enable zero phase
difference) in the loop. The parallel C integrates the current pulses.

>filter, i.e. a transfer function of the form 1/(s*t+1), where "t" is the RC
>time constant. This filter function makes a 2nd order PLL loop which is
>(should be!) unconditionally stable. The reason the simple filter is not
>commonly used is that it limits the parameters that can be varied to meet
>loop specifications (Gardner, _Phaselock Techniques_, Wiley, 1966, has a
>nice exposition in the second chapter). The loop gain is also fixed (i.e.

Even if we need fast settling: the three component network *normally*
shows faster settling but in combination with the automatic
acquisition/tracking selection it's worse than the single capacitor.

>the maximum gain is fixed, and like R, unspecified). This means that for a

The gain is specified, look at the formulae and "fitting parameters"
in 9S12DP256BDGV2.pdf:

Kvco = -120MHz/V * exp((75MHz-f)/120MHz)

Therefore varying between 180MHz/V and 210MHz/V for suitable bus
frequencies.

BTW: I don't understand why Motorola shows the complicated exponential
formula where a simple 200MHz/V linear approximation had less error
that component variations.

The phase comparator has an output current proportional to the phase
with a max. value of 3.5uA or 40uA depending on acq./tracking mode.

The values for the D60A are not shown explicitly in the tabular
electrical specs but in the formulae in appendix A.

And there is really no R.

[lower reference freq. => single cap might not work]

Thanks for the hint - I didn't consider higher multiplication factors
and will likely investigate this in future experiments.

>For the single cap scheme you should be able to put in different size caps
>and see the difference. As the cap increases, at some point, I would
>expect to see overshoot on the XFC pin (but the time-to-lock might become
>too large). (If I had the hardware setup I do some experimenting.)

With the *2 setting (4MHz reference frequency) there was no overshoot
even with 220nF. But I can't preclude overshoot at higher rations due
to the additional delay in the loop.

>Another factor is the noise bandwidth, hence jitter, is minimum when the
>damping is about 0.5, but the penalty for being overdamped is not large. I

I checked open loop jitter of the VCO: in limp home mode I adjusted
the voltage at XFC for ~8MHz E clock. The resulting jitter was less
than 20ns ofer a 10us period.

I don't think that the PLL is a source of much jitter, so if the
voltage at XFC is clean (possible with a single cap), there will not
be much jitter.

>suspect for these reasons Mot recommends the 1 resistor, 2 cap network.
>The problem is that they do not publish the gain (Kvco * Kphasedetector),
>nor an equivalent source resistance, so one is left doing some

See above for gain specification.

>experimenting. AN2219 says that the using the ideas in the AN should not
>be a substitute for measurement.

AN2219 doesn't say much about the PLL behaviour.

>Overall, it looks the one cap scheme ought to be quite satisfactory for
>many situations.
>
>The pullin/lock seems to be the critical factor in for a MCU, i.e. getting
>sufficient stability before coming out of reset. I noticed that the

Since out of reset the clocks are not derived from the PLL in a
HC(S)12 this is unimportant. Software has to wait for stable PLL.

>startup counter has been increased from 4096 in the 912DG128 to 8192 in the
>'9S12.

I don't see the connection between startup counter and PLL.

> Furthermore, the '9S12 also includes a high/low bandwidth filter
>for acquisition/tracking (this is an item that could use something more
>specific that "narrow" and "wide"!).

That's simply switching the phase detector output current between
3.5uA and 40uA and not different from the D60A.

Oliver
--
Oliver Betz, Muenchen




Oliver,

Thanks for the comments. It helped push my thinking.

>The gain is specified, look at the formulae and "fitting parameters"
>in 9S12DP256BDGV2.pdf:

Thanks, I missed the Appendix info! It helps, but raises questions, e.g.
the units on Kphase are ua * Mhz/volt (instead of the usual volts/radian).

>To my knowledge there is a current source, and the current seems to be
>proportional to the phase difference. No "R inside the chip".

Here is my latest thinking.

If the phase detector is a current source (current = K * phase difference),
then the loop will oscillate. There *must* be a "P" component. It doesn't
oscillate, so there is more to it.

If the phase detector (w cap) behaves: voltage = K * phase difference, then
the single cap makes a 1st order loop, which will never overshoot.
However, in this case the current setting (3.5|38ua),as well external
components, would have no effect since it is driven by a voltage source.
Obviously, this is not the case either.

TI's app note (slaa011b) describes the phase detector, which has the
built-in "charge-pump". I expect the '12 has a similar scheme. FETs are
switched to + and gnd in proportion to phase difference. They call this
the charge-pump. A parallel cap averages these current pulses. At a 50%
phase difference (i.e. the "setpoint") the voltage should be 1/2 the
supply, 2.5v--open circuit. Short circuit, the current would be 3.5|38.5
ua tracking|acq modes. That gives an equivalent source of 2.5v though an
apparent resistance of 714K|64.9K *at the control loop freq*.

Unfortunately, the figures don't fit. I took the figures at the bottom of
Table A-16, in 9S12DP256BDGV2.pdf, and worked backwards through the Mot
formulas, to determine fc and Kphase. Kphase matches (344 versus 341). I
then used Gardner's equations to find the "apparent" resistance, I came up
with 874 ohms...only three orders magnitude off ;) I'll keep digging until
I get it sorted out.

>> Furthermore, the '9S12 also includes a high/low bandwidth filter
>>for acquisition/tracking (this is an item that could use something more
>>specific that "narrow" and "wide"!).
>
>That's simply switching the phase detector output current between
>3.5uA and 40uA and not different from the D60A.

Ahah! So wide/narrow is roughly a 11 x change in the gain, hence the
cutoff freq changes. The damping also changes, but if the damping is
designed for the narrow (low current), then the wide (high current) merely
overdamps. Assuming a 2nd order loop, Gardner's approximation indicates
the pullin time should drop by about the square of 11, i.e. 121.

>>Another factor is the noise bandwidth, hence jitter, is minimum when the
>>damping is about 0.5, but the penalty for being overdamped is not large. I
>
>I checked open loop jitter of the VCO: in limp home mode I adjusted
>the voltage at XFC for ~8MHz E clock. The resulting jitter was less
>than 20ns ofer a 10us period.

From the Appendix formula it looks like the pulse-to-pulse jitter is well
below 1 ns at 8 Mhz, contributed by the VCO. If a noisy external reference
were being used, a loop response that is slow might be desired to reduce
the jitter.

>>startup counter has been increased from 4096 in the 912DG128 to 8192 in the
>>'9S12.
>
>I don't see the connection between startup counter and PLL.

You're correct. I confused the slow osc startup problems with PLL lockin. I'm looking at "disciplining" an osc with the gps. The idea is to drive
the micro's clock with the ref osc (10 Mhz) and drive an input capture pin
with the gps timing pulse (100 Hz). Using a HC11 the scheme works as
predicted, but the bus interval is 400 ns. The gps has a sawtooth dither
of +-54 ns, and when using a Rubidium osc for reference, the phase
difference stays within this dither range. For quartz oscs, it goes
outside the gps' dither. At 25 Mhz '9S12's bus interval more than spans
the gps' dither. However, newer gps receivers are coming out with a dither
of around +-20ns. Adding another 20ns dither, via dithering the PLL would
then cover the "dead zone." Hence, my interest the '9S12's PLL behavior.
Regards,

Donald E Haselwood


Donald E Haselwood <> wrote:

>Thanks, I missed the Appendix info! It helps, but raises questions, e.g.
>the units on Kphase are ua * Mhz/volt (instead of the usual volts/radian).

It's a simple integration. Usual VCOs exhibit always voltage
controlled frequency and not voltage controlled phase.

The total loop gain at XFC is 21A/Vs (HC12D60A at 8MHz). Yes, XFC
behaves like a current limited 48mH inductor (1,5mH for the DP256,
1/11 times these values in acquisition mode). Things can be so
simple...

[...]

>If the phase detector is a current source (current = K * phase difference),
>then the loop will oscillate. There *must* be a "P" component. It doesn't
>oscillate, so there is more to it.

You are right, because of the double integration (in the VCO and the
capacitor) and the lack of losses. This seems to be the reason for the
resistor in the PLL filter. Thanks for the hint!

With the "inductor" model of XFC it's even simpler to understand: it's
a parallel resonating circuit and with a 10nF capacitor it will
oscillate at approx. 7kHz 8mV initial amplitude (therefore hard to
observe), only slightly damped by the finite output impedance of the
"current source".

Since the oscillation is small (in the example above, the initial bus
frequency variation will be ~50kHz or 0,6%), it will not hurt in most
cases. The acquisition -> tracking problem with the three component
network is IMHO worse.

Maybe I will measure again the XFC voltage while injecting current
pulses to confirm my assumption.

[...]

>TI's app note (slaa011b) describes the phase detector, which has the
>built-in "charge-pump". I expect the '12 has a similar scheme. FETs are
>switched to + and gnd in proportion to phase difference. They call this

But that TI circuit is more a variable conductance than a variable
(and always high impedance) current source.

Look at

http://www.idt.com/docs/74FCT388915T_AN_78905.pdf

to have a better idea what happens in the HC12.

>ua tracking|acq modes. That gives an equivalent source of 2.5v though an
>apparent resistance of 714K|64.9K *at the control loop freq*.

is IMO not applicable.

[...]

>From the Appendix formula it looks like the pulse-to-pulse jitter is well
>below 1 ns at 8 Mhz, contributed by the VCO. If a noisy external reference
>were being used, a loop response that is slow might be desired to reduce
>the jitter.

Right. Since the "reduced power consumption" oscillator seems to be
very delicate, a slow PLL response can avoid critical situations if
the crystal oscillator is disturbed (e.g. by a indirect coupled ESD
pulse).

Oliver
--
Oliver Betz, Muenchen




Oliver,

Nice work!

>The total loop gain at XFC is 21A/Vs (HC12D60A at 8MHz). Yes, XFC
>behaves like a current limited 48mH inductor (1,5mH for the DP256,
>1/11 times these values in acquisition mode). Things can be so
>simple...

What a clever way to view the XFC pin! Indeed, quite simple. L = 1/K, so
it will vary somewhat due to the exponential in the curve equation for Kv.

As long as the parallel cap is large enough to smooth the phase det pulses
and the filter is good enough approximation for a 2nd order loop--which is
virtually all the situations--this model should work just fine.

>Look at
>http://www.idt.com/docs/74FCT388915T_AN_78905.pdf

The pdf led me to, Gardner, F. (1980). "Charge-pump Phase-lock Loops," IEEE
Trans. COM-28, Nov, pp 1849-1858. Garnder analyzes this situation.
Gardner's article is relatively easy to follow and a worthwhile reference.

BTW, 74FCT388915T_AN_78905.pdf is incorrect with the loop filter analysis.
They have confused voltage with current sources.

The XFC pin with a shunt of a series R & C gives a 2nd order loop. The
additional parallel cap makes a 3rd order loop. In general 3rd ord loops
can be unstable, but in the three element passive case it is always stable
(Gardner).

I also did a US patent search (assignee: Motorola & title: phase detector).
28 hits. No revelations, but shows the progress.

>With the "inductor" model of XFC it's even simpler to understand: it's
>a parallel resonating circuit and with a 10nF capacitor it will
>oscillate at approx. 7kHz 8mV initial amplitude (therefore hard to
>observe), only slightly damped by the finite output impedance of the
>"current source".

Gardner mentions "shunt loading" due to practical circuits, however he is
looking a phase error rather than loop damping. The smaller the C, the
more this "stray" resistance will damp the loop.

Would you say the 8 mv, translates to very roughly 1.6 Mhz vco swing (200
Mhz/volt * 8 mv)? I didn't check the 8 mv peak, but I assume it is the
worst-case current step, i.e. 38.5 ua.

Since there will always be some "stray" resistance (VCO input as well as
phase det) the single cap scheme should "work," i.e. be stable. If pullin
and settling times are not important, then a "big" parallel cap will help
the noise/jitter, too.

Tnanks for raising the issue. I've found this discussion very useful. Regards,

Donald E Haselwood >Maybe I will measure again the XFC voltage while injecting current
>pulses to confirm my assumption.

Let me know how that turns out. If the loop is "damped ringing" as we
expect, the equivalent parallel damping resistance can be estimated by
noting the envelope time constant. My prediction is that it will be close
to the 714K|65K equivalent circuit resistance. Last minute thought--

Thinking in terms of the "inductor model"--Why not make the series cap
*very* big (essentially DC blocking), adjust the Cparallel (with equiv L)
for loop freq, then calc R for whatever damping desired. I think this
would put more cap directly from XFC pin to gnd and help filter the phase
det pulses and high freq noise. Regards,

Donald E Haselwood




Donald E Haselwood <> wrote:

> BTW, 74FCT388915T_AN_78905.pdf is incorrect with the loop filter
> analysis. They have confused voltage with current sources.

It seems to be normal these days to publish data sheets without proof
reading.

For example, Motorola's "MC68HC912D60A technical data" writes: "the
PLL bandwidth is larger in acquisition mode than in tracking by a
ratio of about 3" (should be 11).

[I calculated approx. 7kHz 8mV initial amplitude]

> Would you say the 8 mv, translates to very roughly 1.6 Mhz vco swing
> (200 Mhz/volt * 8 mv)? I didn't check the 8 mv peak, but I assume it
> is the worst-case current step, i.e. 38.5 ua.

No, the calcs were for a D60A in tracking mode, therefore 6MHz/V and
3.5uA. That should be a 50kHz VCO swing or the mentioned 0,6%.

In the meantime I made some brief measurements (always D60A):

I coupled 15Vpp over 4.7MOhms into XFC resulting in roughly 3uApp.

With 11nF there was a hard to detect 15kHz, 5mV. With 1nF 50kHz,
40mVpp nearly undamped. The frequencies are twice my calculations, so
the "inductance" had to be 1/4 - a reason to investigate it further.

Therefore I measured the VCO sensitivity by forcing XFC to a fixed
voltage. It was about 20MHz/V at 8MHz (three times the value from
Motorola's formula) and about 3MHz/V at 3MHz (1/3 of the theoretical
value). That's also the wrong frequency dependence. Maybe the
controller was damaged (I made some ESD test with the board earlier). Important is to know that the oscillation was nearly undamped, IOW
the XFC node shows very high resistance. One should be aware of this
if using a single capacitor.

> Since there will always be some "stray" resistance (VCO input as well
> as phase det) the single cap scheme should "work," i.e. be stable. If
> pullin and settling times are not important, then a "big" parallel cap
> will help the noise/jitter, too.

Remember: due to the 11:1 current change between acquisition and
tracking mode, it takes longer to locked state with the three
component network in most cases.

Workaround: disable "auto", wait for "lock", then wait for approx.
three times the RC time constant, and then switch to "auto" or
acquisition mode. Three times the time constant because the voltage
over R should decay to 1/11 and this takes ln(11)=2,4 times RC. But
the improvement will be marginal.

> Tnanks for raising the issue. I've found this discussion very useful.

Also many thanks - without your comments I never had found that a
single capacitor oscillates.

Oliver




Oliver,

A few additional thoughts:

>For example, Motorola's "MC68HC912D60A technical data" writes: "the
>PLL bandwidth is larger in acquisition mode than in tracking by a
>ratio of about 3" (should be 11).

Actually 3x is close. The bandwidth, or cutoff since it is really LP,
changes by the sqrt(11). But I agree tech data tends to be a bit sloppy.

>With 11nF there was a hard to detect 15kHz, 5mV. With 1nF 50kHz,
>40mVpp nearly undamped. The frequencies are twice my calculations, so
>the "inductance" had to be 1/4 - a reason to investigate it further.

For monitoring the VCO dynamics: How about using putting a scope on the
discriminator of a FM receiver tuned to a harmonic of the bus? Here, the
band is 88-108 Mhz and the discriminators have a bandwidth around 200 Khz.
The harmonic mulitiplies the VCO deviation, so 200 Khz might be a little
narrow...

>Important is to know that the oscillation was nearly undamped, IOW
>the XFC node shows very high resistance. One should be aware of this
>if using a single capacitor.

Also, if phase difference between the PLL and an external reference osc is
important, leakage/bias is important (Gardner points this out). Since the
phase detector current is small to start with it does not take much leakage
to be significant. Near zero phase error, the phase/freq/charge-pump
detectors have a small dead zone--which means the output is
floating--however, Motorola has a patented scheme for eliminating that dead
zone.
Regards,

Don



Donald E Haselwood <> wrote:

> >For example, Motorola's "MC68HC912D60A technical data" writes: "the
> >PLL bandwidth is larger in acquisition mode than in tracking by a
> >ratio of about 3" (should be 11).
>
> Actually 3x is close. The bandwidth, or cutoff since it is really LP,
> changes by the sqrt(11). But I agree tech data tends to be a bit
> sloppy.

I think it's proportional to the current, so 1/11 is correct. The
DP256 docs say:

fc = R * i * Kvco / (2 * Pi * m)

BTW: that also matches my assumption:

L = m / (i * Kvco)

[...]

> For monitoring the VCO dynamics: How about using putting a scope on
> the discriminator of a FM receiver tuned to a harmonic of the bus?

The result was sufficient, since I saw the oscillation and it
correlated with the theory after correcting the VCO sensitivity.

Oliver




Oliver,

>I think it's proportional to the current, so 1/11 is correct. The
>DP256 docs say:
>
>fc = R * i * Kvco / (2 * Pi * m)

The problem with the above is that the C computation also has fc & R in its
denominator. Combine the Mot equations for R and C, and fc becomes
proportional to the square root.

>BTW: that also matches my assumption:
>
>L = m / (i * Kvco)
>
I agree that L = m / (i * Kvco)--therefore--w^2 (radian freq squared) =
1/LC, thus making the bandwidth ratio proportional to the square root of
the gain ratio.

The denominator of the pll (2nd order) loop equation is of the form of a RLC:
s^2 + 2 * q * w + w^2
Where: q is damping factor, w is radian freq.
Since in the single cap case, q is almost zero. The roots are ( s +
j*sqrt(w)) and ( s - j*sqrt(w)).
And in the RLC analogy, w = 1/sqrt(LC) Regards, Donald E Haselwood