S12E128 SPI CPHA logic inverted?

Started by Bruce McMillan October 15, 2003
User feedback.
Porting code from DP256 to E128, it seems that the CPHA logic may be
inverted from that described in the SPI module documentation (and
inverted from the standard implementation of the SPI port on various
versions).

It's possible that the problem is noise on my clock line, but I
suspect not. I don't have a digital Oscilloscope of sufficient speed
to verify my diagnosis, sorry.

bruce.



Yes there is some difference it looks like. I connected MC33993 on
the E128 SPI bus. Not working for me right now.

The E128 SPI bus with CPHA is a confusing. It specify Even or Odd of
SCK clock edges. I don't understand the rational behind it yet. --- In , "Bruce McMillan"
<bruce_at_pocket_neurobics@y...> wrote:
> User feedback.
> Porting code from DP256 to E128, it seems that the CPHA logic may be
> inverted from that described in the SPI module documentation (and
> inverted from the standard implementation of the SPI port on various
> versions).
>
> It's possible that the problem is noise on my clock line, but I
> suspect not. I don't have a digital Oscilloscope of sufficient speed
> to verify my diagnosis, sorry.
>
> bruce.





There are actually four data formats that are selectable with CPHA and
CPOL. It's too hard to explain here, download the SPI Block User Guide,
and read chapter 4. There is a diagram in Figure 4.2 that you can use to
match whatever format your peripheral needs.

I'm not sure if the SPI User Guide is a separate document, I got it as part
of a package of documents describing one particular family.

Alternatively, if you have the 68HC11 Big Pink Book, the SPI works exactly
the same way, and there is the same diagram. Gary Olmstead
Toucan Technology
Ventura CA
www.toucantechnology.com

At 03:06 PM 10/16/03 +0000, you wrote:
>Yes there is some difference it looks like. I connected MC33993 on
>the E128 SPI bus. Not working for me right now.
>
>The E128 SPI bus with CPHA is a confusing. It specify Even or Odd of
>SCK clock edges. I don't understand the rational behind it yet.
>





I need to make a correction to this problem I reported...
The problem exhibits itself when I change the mode (from 1:1
CPOL:CPHA) to write (a single byte) to a 0:0 device - but choosing 0:1
mode will work.

Now, 0:0 mode worked fine when the code executed on a DP256 (making me
think that the problem may be in the E128 chip) but it executes on a
second SPI port. The E128 has just the one SPI port, & so it does all
the work.

In thinking about it, I now believe the problem arises when changing
modes, causing the clock line to go 'idle lo' from 'idle hi' or vice
versa. Checking my code, indeed, I enable the peripheral chip select
BEFORE changing modes, causing an extra clock transition.

Mea Culpa. Change mode, then enable. Change mode, then enable. Change
mode, then enable.

bruce.
--- In , Gary Olmstead <garyolmstead@e...> wrote:
> There are actually four data formats that are selectable with CPHA &
> CPOL. It's too hard to explain here, download the SPI Block User Guide,
> and read chapter 4. There is a diagram in Figure 4.2 that you can
use to
> match whatever format your peripheral needs.
>
> I'm not sure if the SPI User Guide is a separate document, I got it
as part
> of a package of documents describing one particular family.
>
> Alternatively, if you have the 68HC11 Big Pink Book, the SPI works
exactly
> the same way, and there is the same diagram. > Gary Olmstead
> Toucan Technology
> Ventura CA
> www.toucantechnology.com
>
> At 03:06 PM 10/16/03 +0000, you wrote:
> >Yes there is some difference it looks like. I connected MC33993 on
> >the E128 SPI bus. Not working for me right now.
> >
> >The E128 SPI bus with CPHA is a confusing. It specify Even or Odd of
> >SCK clock edges. I don't understand the rational behind it yet.
> >