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I'm trying to generate some code in C for 12DG256 under Codewarrior.
Memory model is large because software has to access a big amount of data in
flash. Test is compiled with -CpPPAGE=0x30 -D_HCS12 -Ml options. At some point of the initialization process and inside PE_low_level_init(void) running from PAGE 0, real timer initialization (generated by processor expert) is called void PE_low_level_init(void) { ..................... /* ### TimerInt "TI1" init code ... */ TI1_Init(); ...................... } TI1_Init() is placed at 3180D2 (PAGE 31) and is succesfully called by means of CALL 0x80D2,31. C code for TI1_Init() is: void TI1_Init(void) { CRGINT_RTIE = 0; /* Disable interrupt */ ................ } Code for the first C instruction is: 3180D2 LDAB #0 3180D4 STAB 0x30 ;PPAGE register is set to 0 3180D6 BCLR 0x38,#128 ;modification of CRGINT and as soon as PAGE is unnecessarily switched to 0 program hangs due improper code execution at page 0. Any clue ?? Jordi Costa |
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Codewarrior,C and large memory model
Started by ●January 7, 2004
Reply by ●January 7, 20042004-01-07
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Hi Jordi. The first internal flash page is page $30. Pages $0 to $2F are external bus. Please see also your project linker prm file to see the memory mapping. Regards, Gilles At 05:07 PM 1/7/2004, you wrote: >I'm trying to generate some code in C for 12DG256 under Codewarrior. >Memory model is large because software has to access a big amount of data >in flash. Test is compiled with -CpPPAGE=0x30 -D_HCS12 -Ml options. > >At some point of the initialization process and inside >PE_low_level_init(void) running from PAGE 0, real timer initialization >(generated by processor expert) is called > >void PE_low_level_init(void) { > ..................... >/* ### TimerInt "TI1" init code ... */ > TI1_Init(); >...................... >} > >TI1_Init() is placed at 3180D2 (PAGE 31) and is succesfully called by >means of CALL 0x80D2,31. > >C code for TI1_Init() is: > >void TI1_Init(void) >{ > CRGINT_RTIE = 0; /* Disable interrupt */ > ................ >} > >Code for the first C instruction is: > >3180D2 LDAB #0 >3180D4 STAB 0x30 ;PPAGE register is set to 0 >3180D6 BCLR 0x38,#128 ;modification of CRGINT > >and as soon as PAGE is unnecessarily switched to 0 program hangs due >improper code execution at page 0. > >Any clue ?? > >Jordi Costa > > >--------------------To learn more >about Motorola Microcontrollers, please visit >http://www.motorola.com/mcu >o learn more about Motorola Microcontrollers, please visit >http://www.motorola.com/mcu > > |
Reply by ●January 7, 20042004-01-07
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Hi again. Also which code generates this? > >3180D2 LDAB #0 > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > >3180D6 BCLR 0x38,#128 ;modification of CRGINT STAB 0x30 switches to page 0 and PC at 0080D6 is fetched instead of 3180D6. PPAGE is transparently handled by the compiler through CALL/RTC instructions. Regards, Gilles At 05:28 PM 1/7/2004, you wrote: >Hi Jordi. > >The first internal flash page is page $30. >Pages $0 to $2F are external bus. > >Please see also your project linker prm file to see the memory mapping. > >Regards, >Gilles >At 05:07 PM 1/7/2004, you wrote: > >I'm trying to generate some code in C for 12DG256 under Codewarrior. > >Memory model is large because software has to access a big amount of data > >in flash. Test is compiled with -CpPPAGE=0x30 -D_HCS12 -Ml options. > > > >At some point of the initialization process and inside > >PE_low_level_init(void) running from PAGE 0, real timer initialization > >(generated by processor expert) is called > > > >void PE_low_level_init(void) { > > ..................... > >/* ### TimerInt "TI1" init code ... */ > > TI1_Init(); > >...................... > >} > > > >TI1_Init() is placed at 3180D2 (PAGE 31) and is succesfully called by > >means of CALL 0x80D2,31. > > > >C code for TI1_Init() is: > > > >void TI1_Init(void) > >{ > > CRGINT_RTIE = 0; /* Disable interrupt */ > > ................ > >} > > > >Code for the first C instruction is: > > > >3180D2 LDAB #0 > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > > >and as soon as PAGE is unnecessarily switched to 0 program hangs due > >improper code execution at page 0. > > > >Any clue ?? > > > >Jordi Costa > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >--------------------To learn more > >about Motorola Microcontrollers, please visit > >http://www.motorola.com/mcu > >o learn more about Motorola Microcontrollers, please visit > >http://www.motorola.com/mcu > > > > > > > >--------------------To learn more >about Motorola Microcontrollers, please visit >http://www.motorola.com/mcu >o learn more about Motorola Microcontrollers, please visit >http://www.motorola.com/mcu > > |
Reply by ●January 7, 20042004-01-07
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Gilles, 3180D2 LDAB #0 3180D4 STAB 0x30 3180D6 BCLR 0x38,#128 is the code generated for the C instruction CRGINT_RTIE = 0; Regards, Jordi ----- Original Message ----- From: "Gilles Blanquin" <> To: <> Sent: Wednesday, January 07, 2004 5:46 PM Subject: Re: [68HC12] Codewarrior,C and large memory model > Hi again. > > Also which code generates this? > > > >3180D2 LDAB #0 > > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > STAB 0x30 switches to page 0 and PC at 0080D6 is fetched instead of 3180D6. > > PPAGE is transparently handled by the compiler through CALL/RTC instructions. > > Regards, > Gilles > At 05:28 PM 1/7/2004, you wrote: > >Hi Jordi. > > > >The first internal flash page is page $30. > >Pages $0 to $2F are external bus. > > > >Please see also your project linker prm file to see the memory mapping. > > > >Regards, > >Gilles > > > > > >At 05:07 PM 1/7/2004, you wrote: > > >I'm trying to generate some code in C for 12DG256 under Codewarrior. > > >Memory model is large because software has to access a big amount of data > > >in flash. Test is compiled with -CpPPAGE=0x30 -D_HCS12 -Ml options. > > > > > >At some point of the initialization process and inside > > >PE_low_level_init(void) running from PAGE 0, real timer initialization > > >(generated by processor expert) is called > > > > > >void PE_low_level_init(void) { > > > ..................... > > >/* ### TimerInt "TI1" init code ... */ > > > TI1_Init(); > > >...................... > > >} > > > > > >TI1_Init() is placed at 3180D2 (PAGE 31) and is succesfully called by > > >means of CALL 0x80D2,31. > > > > > >C code for TI1_Init() is: > > > > > >void TI1_Init(void) > > >{ > > > CRGINT_RTIE = 0; /* Disable interrupt */ > > > ................ > > >} > > > > > >Code for the first C instruction is: > > > > > >3180D2 LDAB #0 > > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > > > > >and as soon as PAGE is unnecessarily switched to 0 program hangs due > > >improper code execution at page 0. > > > > > >Any clue ?? > > > > > >Jordi Costa > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >--------------------To learn more > > >about Motorola Microcontrollers, please visit > > >http://www.motorola.com/mcu > > >o learn more about Motorola Microcontrollers, please visit > > >http://www.motorola.com/mcu > > > > > > > > > > > > > > > > > >--------------------To learn more > >about Motorola Microcontrollers, please visit > >http://www.motorola.com/mcu > >o learn more about Motorola Microcontrollers, please visit > >http://www.motorola.com/mcu > > > > > > > > --------------------To learn more about Motorola Microcontrollers, please visit > http://www.motorola.com/mcu > o learn more about Motorola Microcontrollers, please visit > http://www.motorola.com/mcu |
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Reply by ●January 7, 20042004-01-07
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Seems like the CRGINT _IO_AT_ statement is incorrectly specifying the address 0x30. --- In , "Jordi Costa" <bvjordi@b...> wrote: > Gilles, > > 3180D2 LDAB #0 > 3180D4 STAB 0x30 > 3180D6 BCLR 0x38,#128 > > is the code generated for the C instruction > > CRGINT_RTIE = 0; > > Regards, > > Jordi > > ----- Original Message ----- > From: "Gilles Blanquin" <gblanquin@m...> > To: <> > Sent: Wednesday, January 07, 2004 5:46 PM > Subject: Re: [68HC12] Codewarrior,C and large memory model > > Hi again. > > > > Also which code generates this? > > > > > >3180D2 LDAB #0 > > > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > > > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > > > STAB 0x30 switches to page 0 and PC at 0080D6 is fetched instead of > 3180D6. > > > > PPAGE is transparently handled by the compiler through CALL/RTC > instructions. > > > > Regards, > > Gilles > > > > > > At 05:28 PM 1/7/2004, you wrote: > > >Hi Jordi. > > > > > >The first internal flash page is page $30. > > >Pages $0 to $2F are external bus. > > > > > >Please see also your project linker prm file to see the memory mapping. > > > > > >Regards, > > >Gilles > > > > > > > > >At 05:07 PM 1/7/2004, you wrote: > > > >I'm trying to generate some code in C for 12DG256 under Codewarrior. > > > >Memory model is large because software has to access a big amount of > data > > > >in flash. Test is compiled with -CpPPAGE=0x30 -D_HCS12 -Ml options. > > > > > > > >At some point of the initialization process and inside > > > >PE_low_level_init(void) running from PAGE 0, real timer initialization > > > >(generated by processor expert) is called > > > > > > > >void PE_low_level_init(void) { > > > > ..................... > > > >/* ### TimerInt "TI1" init code ... */ > > > > TI1_Init(); > > > >...................... > > > >} > > > > > > > >TI1_Init() is placed at 3180D2 (PAGE 31) and is succesfully called by > > > >means of CALL 0x80D2,31. > > > > > > > >C code for TI1_Init() is: > > > > > > > >void TI1_Init(void) > > > >{ > > > > CRGINT_RTIE = 0; /* Disable interrupt */ > > > > ................ > > > >} > > > > > > > >Code for the first C instruction is: > > > > > > > >3180D2 LDAB #0 > > > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > > > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > > > > > > >and as soon as PAGE is unnecessarily switched to 0 program hangs due > > > >improper code execution at page 0. > > > > > > > >Any clue ?? > > > > > > > >Jordi Costa > > > >bvjordi@b... > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >--------------------To learn more > > > >about Motorola Microcontrollers, please visit > > > >http://www.motorola.com/mcu > > > >o learn more about Motorola Microcontrollers, please visit > > > >http://www.motorola.com/mcu > > > > > > > > > > > > > > > > > > > > > > > > >--------------------To learn more > > >about Motorola Microcontrollers, please visit > > >http://www.motorola.com/mcu > > >o learn more about Motorola Microcontrollers, please visit > > >http://www.motorola.com/mcu > > > > > > > > > > > > > > > > > > --------------------To learn more > about Motorola Microcontrollers, please visit > > http://www.motorola.com/mcu > > o learn more about Motorola Microcontrollers, please visit > > http://www.motorola.com/mcu > > > > > > > > > > |
Reply by ●January 7, 20042004-01-07
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No. The code LDDA #0, STAA 0x30 that changes the PAGE register is
inserted each time that a value is assigned to a variable. For example, in: void _EntryPoint(void) ................ INITRM=1; /* Set the RAM map position */ I have: ............... C004 LDAB #1 ; "1" C006 LDDA #0 ; desired PAGE ( 0) C008 STAA 0x30 ; PPAGE to 0 C00A STAB 0x10 ; INITRM to 1 In this case program does not hang due PAGE change because code of this section is running in page 0. Jordi ----- Original Message ----- From: "varneybob" <> To: <> Sent: Wednesday, January 07, 2004 6:37 PM Subject: [68HC12] Re: Codewarrior,C and large memory model > Seems like the CRGINT _IO_AT_ statement is incorrectly specifying the > address 0x30. > > --- In , "Jordi Costa" <bvjordi@b...> wrote: > > Gilles, > > > > 3180D2 LDAB #0 > > 3180D4 STAB 0x30 > > 3180D6 BCLR 0x38,#128 > > > > is the code generated for the C instruction > > > > CRGINT_RTIE = 0; > > > > Regards, > > > > Jordi > > > > ----- Original Message ----- > > From: "Gilles Blanquin" <gblanquin@m...> > > To: <> > > Sent: Wednesday, January 07, 2004 5:46 PM > > Subject: Re: [68HC12] Codewarrior,C and large memory model > > > > > > > Hi again. > > > > > > Also which code generates this? > > > > > > > >3180D2 LDAB #0 > > > > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > > > > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > > > > > STAB 0x30 switches to page 0 and PC at 0080D6 is fetched instead > of > > 3180D6. > > > > > > PPAGE is transparently handled by the compiler through CALL/RTC > > instructions. > > > > > > Regards, > > > Gilles > > > > > > > > > At 05:28 PM 1/7/2004, you wrote: > > > >Hi Jordi. > > > > > > > >The first internal flash page is page $30. > > > >Pages $0 to $2F are external bus. > > > > > > > >Please see also your project linker prm file to see the memory > mapping. > > > > > > > >Regards, > > > >Gilles > > > > > > > > > > > >At 05:07 PM 1/7/2004, you wrote: > > > > >I'm trying to generate some code in C for 12DG256 under > Codewarrior. > > > > >Memory model is large because software has to access a big > amount of > > data > > > > >in flash. Test is compiled with -CpPPAGE=0x30 -D_HCS12 -Ml > options. > > > > > > > > > >At some point of the initialization process and inside > > > > >PE_low_level_init(void) running from PAGE 0, real timer > initialization > > > > >(generated by processor expert) is called > > > > > > > > > >void PE_low_level_init(void) { > > > > > ..................... > > > > >/* ### TimerInt "TI1" init code ... */ > > > > > TI1_Init(); > > > > >...................... > > > > >} > > > > > > > > > >TI1_Init() is placed at 3180D2 (PAGE 31) and is succesfully > called by > > > > >means of CALL 0x80D2,31. > > > > > > > > > >C code for TI1_Init() is: > > > > > > > > > >void TI1_Init(void) > > > > >{ > > > > > CRGINT_RTIE = 0; /* Disable interrupt */ > > > > > ................ > > > > >} > > > > > > > > > >Code for the first C instruction is: > > > > > > > > > >3180D2 LDAB #0 > > > > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > > > > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > > > > > > > > >and as soon as PAGE is unnecessarily switched to 0 program > hangs due > > > > >improper code execution at page 0. > > > > > > > > > >Any clue ?? > > > > > > > > > >Jordi Costa > > > > >bvjordi@b... > > > > > > > > > > |
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Reply by ●January 8, 20042004-01-08
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Hi Jordi. This latest decoded section is fine, because executed from a non banked area. You have to use a runtime to access banked data, like "datapage.c". If you use banked (const) data, I propose you to see the delivered project in CodeWarrior V3.0 for HC(S)12 : Stationery\HCS12\Board Support\cml12s-dp256\cml12s-dp256_banked_data_code_and_const.mcp I send you this project off line, in case you use a previous CodeWarrior release. You can also send me directly an extract of your project that I could debug and setup if necessary. Regards, Gilles At 07:26 PM 1/7/2004, you wrote: >No. The code LDDA #0, STAA 0x30 that changes the PAGE register is inserted >each time that a value is assigned to a variable. For example, in: > >void _EntryPoint(void) >................ >INITRM=1; /* Set the RAM map position */ > >I have: >............... >C004 LDAB #1 ; "1" >C006 LDDA #0 ; desired PAGE ( 0) >C008 STAA 0x30 ; PPAGE to 0 >C00A STAB 0x10 ; INITRM to 1 > >In this case program does not hang due PAGE change because code of this >section is running in page 0. > >Jordi > >----- Original Message ----- >From: "varneybob" <> >To: <> >Sent: Wednesday, January 07, 2004 6:37 PM >Subject: [68HC12] Re: Codewarrior,C and large memory model > > Seems like the CRGINT _IO_AT_ statement is incorrectly specifying the > > address 0x30. > > > > --- In , "Jordi Costa" <bvjordi@b...> wrote: > > > Gilles, > > > > > > 3180D2 LDAB #0 > > > 3180D4 STAB 0x30 > > > 3180D6 BCLR 0x38,#128 > > > > > > is the code generated for the C instruction > > > > > > CRGINT_RTIE = 0; > > > > > > Regards, > > > > > > Jordi > > > > > > ----- Original Message ----- > > > From: "Gilles Blanquin" <gblanquin@m...> > > > To: <> > > > Sent: Wednesday, January 07, 2004 5:46 PM > > > Subject: Re: [68HC12] Codewarrior,C and large memory model > > > > > > > > > > Hi again. > > > > > > > > Also which code generates this? > > > > > > > > > >3180D2 LDAB #0 > > > > > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > > > > > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > > > > > > > STAB 0x30 switches to page 0 and PC at 0080D6 is fetched instead > > of > > > 3180D6. > > > > > > > > PPAGE is transparently handled by the compiler through CALL/RTC > > > instructions. > > > > > > > > Regards, > > > > Gilles > > > > > > > > > > > > At 05:28 PM 1/7/2004, you wrote: > > > > >Hi Jordi. > > > > > > > > > >The first internal flash page is page $30. > > > > >Pages $0 to $2F are external bus. > > > > > > > > > >Please see also your project linker prm file to see the memory > > mapping. > > > > > > > > > >Regards, > > > > >Gilles > > > > > > > > > > > > > > >At 05:07 PM 1/7/2004, you wrote: > > > > > >I'm trying to generate some code in C for 12DG256 under > > Codewarrior. > > > > > >Memory model is large because software has to access a big > > amount of > > > data > > > > > >in flash. Test is compiled with -CpPPAGE=0x30 -D_HCS12 -Ml > > options. > > > > > > > > > > > >At some point of the initialization process and inside > > > > > >PE_low_level_init(void) running from PAGE 0, real timer > > initialization > > > > > >(generated by processor expert) is called > > > > > > > > > > > >void PE_low_level_init(void) { > > > > > > ..................... > > > > > >/* ### TimerInt "TI1" init code ... */ > > > > > > TI1_Init(); > > > > > >...................... > > > > > >} > > > > > > > > > > > >TI1_Init() is placed at 3180D2 (PAGE 31) and is succesfully > > called by > > > > > >means of CALL 0x80D2,31. > > > > > > > > > > > >C code for TI1_Init() is: > > > > > > > > > > > >void TI1_Init(void) > > > > > >{ > > > > > > CRGINT_RTIE = 0; /* Disable interrupt */ > > > > > > ................ > > > > > >} > > > > > > > > > > > >Code for the first C instruction is: > > > > > > > > > > > >3180D2 LDAB #0 > > > > > >3180D4 STAB 0x30 ;PPAGE register is set to 0 > > > > > >3180D6 BCLR 0x38,#128 ;modification of CRGINT > > > > > > > > > > > >and as soon as PAGE is unnecessarily switched to 0 program > > hangs due > > > > > >improper code execution at page 0. > > > > > > > > > > > >Any clue ?? > > > > > > > > > > > >Jordi Costa > > > > > >bvjordi@b... > > > > > > > > > > > > >--------------------To learn more >about Motorola Microcontrollers, please visit >http://www.motorola.com/mcu >o learn more about Motorola Microcontrollers, please visit >http://www.motorola.com/mcu > > |
Reply by ●January 8, 20042004-01-08
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Hi Gilles, Thank you for the information and support. I will try to follow your guidelines. Jordi ----- Original Message ----- From: "Gilles Blanquin" <> To: <> Sent: Thursday, January 08, 2004 9:47 AM Subject: Re: [68HC12] Re: Codewarrior,C and large memory model > > Hi Jordi. > > This latest decoded section is fine, because executed from a non banked area. > You have to use a runtime to access banked data, like "datapage.c". > > If you use banked (const) data, I propose you to see the delivered project > in CodeWarrior V3.0 for HC(S)12 : > > Stationery\HCS12\Board > Support\cml12s-dp256\cml12s-dp256_banked_data_code_and_const.mcp > > I send you this project off line, in case you use a previous CodeWarrior > release. > > You can also send me directly an extract of your project that I could debug > and setup if necessary. > > Regards, > Gilles > > At 07:26 PM 1/7/2004, you wrote: > >No. The code LDDA #0, STAA 0x30 that changes the PAGE register is inserted > >each time that a value is assigned to a variable. For example, in: > > > >void _EntryPoint(void) > >................ > >INITRM=1; /* Set the RAM map position */ > > > >I have: > >............... > >C004 LDAB #1 ; "1" > >C006 LDDA #0 ; desired PAGE ( 0) > >C008 STAA 0x30 ; PPAGE to 0 > >C00A STAB 0x10 ; INITRM to 1 > > > >In this case program does not hang due PAGE change because code of this > >section is running in page 0. > > > >Jordi |
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Reply by ●January 8, 20042004-01-08
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Hi Gilles & Jordi, as far as I know, Unis does not support the large memory model :-(. If I get the situation correct, then the complete code of Jordi's application is outside of the 0x8000..0xBFFF window (int 0x4000..0x7FFF or 0xC000..0xFFFF)). So the application consist of less that 16k code and up to 240k of constant data. If this is not correct, use "-CpPPAGE=RUNTIME " (which generates a lot more and slower code). Ok, back to the problem, the unis derivative header files do not explicitly specify that the variables are not paged variables, which is the default in the large memory model. (Note that the compiler on his side could theoretically detect this from the address, but he does not do this.) See the code snippet here how to avoid the unnecessary (inefficient, but at least still working) page setting: volatile unsigned char io_port10 @10; volatile unsigned char __near io_port11 @11; void test10(void) { io_port10= 10; } void test11(void) { io_port11= 11; } This generates with "-lasm -CpPPAGE=0x30 -D_HCS12 -Ml" 5: io_port10= 10; 0000 c60a LDAB #10 0002 8600 LDAA #PAGE(io_port10) 0004 5a30 STAA 48 0006 5b00 STAB io_port10 6: } 0008 0a RTC 7: void test11(void) { 8: io_port11= 11; 0000 c60b LDAB #11 0002 5b00 STAB io_port11 9: } 0004 0a RTC 10: #if 0 The large memory model is handy to quickly write code which has access to all the data. However the code is considerably larger and slower than in the banked memory model. So if you can isolate the access to your paged constants, consider explicitly use far pointers in this area and the banked memory model. PS: The option "-CpPPAGE=0x30 " implies that the PPAGE can be freely changed. So all the code has to be outside of the 0x8000..0xBFFF window. Bye Daniel > -----Original Message----- > From: Jordi Costa [mailto:] > Sent: Thursday, January 08, 2004 10:22 > To: > Subject: Re: [68HC12] Re: Codewarrior,C and large memory model > Hi Gilles, > > Thank you for the information and support. I will try to follow your > guidelines. > > Jordi > > ----- Original Message ----- > From: "Gilles Blanquin" <> > To: <> > Sent: Thursday, January 08, 2004 9:47 AM > Subject: Re: [68HC12] Re: Codewarrior,C and large memory model > > > > Hi Jordi. > > > > This latest decoded section is fine, because executed from a non banked > area. > > You have to use a runtime to access banked data, like "datapage.c". > > > > If you use banked (const) data, I propose you to see the delivered project > > in CodeWarrior V3.0 for HC(S)12 : > > > > Stationery\HCS12\Board > > Support\cml12s-dp256\cml12s-dp256_banked_data_code_and_const.mcp > > > > I send you this project off line, in case you use a previous CodeWarrior > > release. > > > > You can also send me directly an extract of your project that I could > debug > > and setup if necessary. > > > > Regards, > > Gilles > > > > > > > > At 07:26 PM 1/7/2004, you wrote: > > >No. The code LDDA #0, STAA 0x30 that changes the PAGE register is > inserted > > >each time that a value is assigned to a variable. For example, in: > > > > > >void _EntryPoint(void) > > >................ > > >INITRM=1; /* Set the RAM map position */ > > > > > >I have: > > >............... > > >C004 LDAB #1 ; "1" > > >C006 LDDA #0 ; desired PAGE ( 0) > > >C008 STAA 0x30 ; PPAGE to 0 > > >C00A STAB 0x10 ; INITRM to 1 > > > > > >In this case program does not hang due PAGE change because code of this > > >section is running in page 0. > > > > > >Jordi > > --------------------To learn more about Motorola Microcontrollers, please visit > http://www.motorola.com/mcu > o learn more about Motorola Microcontrollers, please visit > http://www.motorola.com/mcu > |
Reply by ●January 8, 20042004-01-08
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Hi Daniel, I think you are right and compiler was considering all variables as paged because Processor Expert header files do not specify near. By other side I was confused about the correct usage of "-CpPPAGE=RUNTIME ". Now I am compiling under banked memory model and code runs properly while it is smaller and faster because unnecessary PPAGE manipulations are not present. I have been also doing some experimentation accessing "far data" following Gilles suggestions and they work properly through datapage as expected. So, the correct way to work is banked memory model and use/access "far data" only when necessary. Best regards and thanks for your help. Jordi ----- Original Message ----- From: "Daniel Friederich" <> To: <> Sent: Thursday, January 08, 2004 2:36 PM Subject: RE: [68HC12] Re: Codewarrior,C and large memory model > Hi Gilles & Jordi, > > as far as I know, Unis does not support the large memory model :-(. > > If I get the situation correct, then the complete code of Jordi's application is outside of the 0x8000..0xBFFF window > (int 0x4000..0x7FFF or 0xC000..0xFFFF)). So the application consist of less that 16k code and up to 240k of constant data. > If this is not correct, use "-CpPPAGE=RUNTIME " (which generates a lot more and slower code). > > Ok, back to the problem, the unis derivative header files do not explicitly specify > that the variables are not paged variables, which is the default in the large memory model. > (Note that the compiler on his side could theoretically detect this from the address, but he does not do this.) > > See the code snippet here how to avoid the unnecessary (inefficient, but at least still working) page setting: > > volatile unsigned char io_port10 @10; > volatile unsigned char __near io_port11 @11; > > void test10(void) { > io_port10= 10; > } > void test11(void) { > io_port11= 11; > } > > This generates with "-lasm -CpPPAGE=0x30 -D_HCS12 -Ml" > > 5: io_port10= 10; > 0000 c60a LDAB #10 > 0002 8600 LDAA #PAGE(io_port10) > 0004 5a30 STAA 48 > 0006 5b00 STAB io_port10 > 6: } > 0008 0a RTC > 7: void test11(void) { > 8: io_port11= 11; > 0000 c60b LDAB #11 > 0002 5b00 STAB io_port11 > 9: } > 0004 0a RTC > 10: #if 0 > > The large memory model is handy to quickly write code which has access to all the data. > However the code is considerably larger and slower than in the banked memory model. So if you can isolate the access to > your paged constants, consider explicitly use far pointers in this area and the banked memory model. > PS: The option "-CpPPAGE=0x30 " implies that the PPAGE can be freely changed. So all the code has to be outside of the > 0x8000..0xBFFF window. > > Bye > > Daniel > > -----Original Message----- > > From: Jordi Costa [mailto:] > > Sent: Thursday, January 08, 2004 10:22 > > To: > > Subject: Re: [68HC12] Re: Codewarrior,C and large memory model > > > > > > Hi Gilles, > > > > Thank you for the information and support. I will try to follow your > > guidelines. > > > > Jordi > > > > ----- Original Message ----- > > From: "Gilles Blanquin" <> > > To: <> > > Sent: Thursday, January 08, 2004 9:47 AM > > Subject: Re: [68HC12] Re: Codewarrior,C and large memory model > > > > > > > > > > Hi Jordi. > > > > > > This latest decoded section is fine, because executed from a non banked > > area. > > > You have to use a runtime to access banked data, like "datapage.c". > > > > > > If you use banked (const) data, I propose you to see the delivered project > > > in CodeWarrior V3.0 for HC(S)12 : > > > > > > Stationery\HCS12\Board > > > Support\cml12s-dp256\cml12s-dp256_banked_data_code_and_const.mcp > > > > > > I send you this project off line, in case you use a previous CodeWarrior > > > release. > > > > > > You can also send me directly an extract of your project that I could > > debug > > > and setup if necessary. > > > > > > Regards, > > > Gilles > > > |
