Re: AN2153 Boot loader note about bug in initial silicon

Started by Gordon Doughman January 28, 2004
Rod/Doron,

This problem was only present in the 0K36N mask set.

Regards,
Gordon

Doron Fael wrote:

>Rod,
>
>The extra NOPs are indeed required for the PLL.
>
>After changing the PLL registers of the HCS12, there is a delay before the
>LOCK bit correctly reflects that the PLL is not locked. The NOPs are meant
>to generate a short delay after changing the PLL registers and before
>testing the LOCK bit, in order to make sure the LOCK bit will initially
>reflect the correct not-locked condition, so the code won't continue
>forward before the PLL is locked and the appropriate new operation
>frequency has stabilized and is ready to be selected and fed to the HCS12
>resources.
>
>At Noahu we recommend to our customers an even more strict algorithm, that
>waits for the LOCK bit to read as locked for 10 consecutive times, before
>deciding the PLL is indeed locked, and it is safe to select it to feed the
>new operation frequency to the HCS12 resources.
>
>Hope this helps,
>Doron
>Nohau Corporation
>HC12 In-Circuit Emulators
>www.nohau.com/emul12pc.html
>
>At 13:30 27/01/2004 -0500, you wrote:
>
>>Does anyone know why the comment "nops required for bug in initial
>>silicon" is present?
>>( about nine lines after the MoveMore label). I am assuming it has to
>>do with locking the PLL which we don't use but
>>I appreciate if someone can confirm it.
>>
>>Rod Niner
>>GSE Scales
>>42860 Nine Mile Road
>>Novi, MI 48375-4122
>>ph: 248.596.3350
>>
>>
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>>
> >--------------------To learn more about Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu
>o learn more about Motorola Microcontrollers, please visit
>http://www.motorola.com/mcu >
>

--
===============================================================
Gordon Doughman Ph: 937-438-6811
Motorola Semiconductor Fax: 937-434-7457
Field Applications Engineer Pager: 800-759-8352 Pin: 1304089
Suite 175
3131 Newmark Drive
Miamisburg, OH 45342

Check out my HC12 book at:
http://www.rtcbooks.com/programming.php




Gordon,

We certainly experience it also with the 0K79X and 1K79X. We have had
several cases of this problem showing up at customer sites with these
mask-sets.

Hope this helps,
Doron
Nohau Corporation
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html

At 09:52 28/01/2004 -0500, you wrote:
>Rod/Doron,
>
>This problem was only present in the 0K36N mask set.
>
>Regards,
>Gordon
>
>Doron Fael wrote:
>
> >Rod,
> >
> >The extra NOPs are indeed required for the PLL.
> >
> >After changing the PLL registers of the HCS12, there is a delay before the
> >LOCK bit correctly reflects that the PLL is not locked. The NOPs are meant
> >to generate a short delay after changing the PLL registers and before
> >testing the LOCK bit, in order to make sure the LOCK bit will initially
> >reflect the correct not-locked condition, so the code won't continue
> >forward before the PLL is locked and the appropriate new operation
> >frequency has stabilized and is ready to be selected and fed to the HCS12
> >resources.
> >
> >At Noahu we recommend to our customers an even more strict algorithm, that
> >waits for the LOCK bit to read as locked for 10 consecutive times, before
> >deciding the PLL is indeed locked, and it is safe to select it to feed the
> >new operation frequency to the HCS12 resources.
> >
> >Hope this helps,
> >Doron
> >Nohau Corporation
> >HC12 In-Circuit Emulators
> >www.nohau.com/emul12pc.html
> >
> >At 13:30 27/01/2004 -0500, you wrote:
> >
> >>Does anyone know why the comment "nops required for bug in initial
> >>silicon" is present?
> >>( about nine lines after the MoveMore label). I am assuming it has to
> >>do with locking the PLL which we don't use but
> >>I appreciate if someone can confirm it.
> >>
> >>Rod Niner
> >>GSE Scales
> >>42860 Nine Mile Road
> >>Novi, MI 48375-4122
> >>ph: 248.596.3350
> >>
>
>--
>===============================================================
>Gordon Doughman Ph: 937-438-6811
>Motorola Semiconductor Fax: 937-434-7457
>Field Applications Engineer Pager: 800-759-8352 Pin: 1304089
>Suite 175
>3131 Newmark Drive
>Miamisburg, OH 45342
>
>Check out my HC12 book at:
>http://www.rtcbooks.com/programming.php





PLLs are a continuing challenge for circuit designers. This can be seen by
the number of books just about PLLs and experience over the years.

Doron's description of our lock test was a little simpler than the actual
test that the current Nohau software uses. I'd like to explain why we use
this method and how it is implemented.

This test was intended to be immune to the PLL design features that Doron
and I have seen over the years. Since the implementation is only slightly
longer the simplest lock tests, I recommend using it without simplification.

At the heart of a PLL is a "phase detector" that compares the reference
frequency divided by the reference divider with the oscillator frequency
divided by the other divider. One of the PLL design challenges is
correctly indicating when the PLL is locked through all the states of the
phase detector. I have seen some otherwise satisfactory designs that did
not meet this challenge.

To avoid most of the problems that show up in lock indication logic, what
we do is:

1. Calculate the period of the phase detector. ( Ext clock / Reference
divisor ) Usually this can be calculated at compile or assemble time

2. Turn on the PLL, but don't select it.

3. If the time since the PLL was turned is too long (1 second or 1000 phase
detector periods, your choice), declare a failure to lock and give up.

4. Wait for the lock bit to be one.

5. Keep testing the lock bit for 1 for 10 to 100 periods of the phase detector.

6. If the lock bit goes to 0 during this wait, go back to step 3.

7. Switch the system clock to the PLL

A wait of 10 periods of the phase detector is conservative. A wait of 100
periods is very conservative.

I'd like to emphasize that when a PLL is not locked, it often varies its
frequency very rapidly, and most processor designs just plain stop
operating correctly when they get this sort of erratic clock.

If you switch system clock to an unlocked PLL you often get a system that
fails to execute instructions correctly.

Steve

At 07:25 AM 1/28/2004, you wrote:
>Gordon,
>
>We certainly experience it also with the 0K79X and 1K79X. We have had
>several cases of this problem showing up at customer sites with these
>mask-sets.
>
>Hope this helps,
>Doron
>Nohau Corporation
>HC12 In-Circuit Emulators
>www.nohau.com/emul12pc.html
>
>At 09:52 28/01/2004 -0500, you wrote:
> >Rod/Doron,
> >
> >This problem was only present in the 0K36N mask set.
> >
> >Regards,
> >Gordon
> >
> >Doron Fael wrote:
> >
> > >Rod,
> > >
> > >The extra NOPs are indeed required for the PLL.
> > >
> > >After changing the PLL registers of the HCS12, there is a delay before the
> > >LOCK bit correctly reflects that the PLL is not locked. The NOPs are meant
> > >to generate a short delay after changing the PLL registers and before
> > >testing the LOCK bit, in order to make sure the LOCK bit will initially
> > >reflect the correct not-locked condition, so the code won't continue
> > >forward before the PLL is locked and the appropriate new operation
> > >frequency has stabilized and is ready to be selected and fed to the HCS12
> > >resources.
> > >
> > >At Noahu we recommend to our customers an even more strict algorithm, that
> > >waits for the LOCK bit to read as locked for 10 consecutive times, before
> > >deciding the PLL is indeed locked, and it is safe to select it to feed the
> > >new operation frequency to the HCS12 resources.
> > >
> > >Hope this helps,
> > >Doron
> > >Nohau Corporation
> > >HC12 In-Circuit Emulators
> > >www.nohau.com/emul12pc.html
> > >
> > >At 13:30 27/01/2004 -0500, you wrote:
> > >
> > >>Does anyone know why the comment "nops required for bug in initial
> > >>silicon" is present?
> > >>( about nine lines after the MoveMore label). I am assuming it has to
> > >>do with locking the PLL which we don't use but
> > >>I appreciate if someone can confirm it.
> > >>
> > >>Rod Niner
> > >>GSE Scales
> > >>42860 Nine Mile Road
> > >>Novi, MI 48375-4122
> > >>ph: 248.596.3350
> > >>
> >
> >--
> >===============================================================
> >Gordon Doughman Ph: 937-438-6811
> >Motorola Semiconductor Fax: 937-434-7457
> >Field Applications Engineer Pager: 800-759-8352 Pin: 1304089
> >Suite 175
> >3131 Newmark Drive
> >Miamisburg, OH 45342
> >
> >Check out my HC12 book at:
> ><http://www.rtcbooks.com/programm" target="_blank" rel="nofollow">http://www.rtcbooks.com/programming.php>http://www.rtcbooks.com/programm
> ing.php >
>--------------------To learn more
>about Motorola Microcontrollers, please visit
><http://www.motorola.com/mcu" target="_blank" rel="nofollow">http://www.motorola.com/mcu>http://www.motorola.com/mcu
>o learn more about Motorola Microcontrollers, please visit
><http://www.motorola.com/mcu" target="_blank" rel="nofollow">http://www.motorola.com/mcu>http://www.motorola.com/mcu >
>
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Steve Russell mailto:
Senior Software Design Engineer http://www.nohau.com
Nohau Corporation phone: (408)866-1820 ext. 1873
51 East Campbell Avenue fax: (408)378-7869
Campbell, CA 95008
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