Port IRQ's

Started by Graham Tricker February 20, 2004
Hi

I have a problem with interrupts on port P on a MC9S12DP256. I have two
clock signals on P2 and P7 running at 19200 baud. I am interrupting on the
rising edge of each signal, I can run each of these independently with no
problems. When I run both interrupts simultaneously I appear to lose
interrupt flags for each signal. Below is my interrupt service routine
which I have stripped to the basics of entering the routine clearing the
flag and toggling a port pin for each channel. I think my problem is that
the two clock signals occasionally coincide and only generate one interrupt
flag and the other gets lost somewhere or just ignored. My thinking at the
minute is to move one of the clock signals to another port but any other
suggestions would be much appreciated.

interrupt void PortP_ISR (void)

{

// ChannelA IRQ
// ---------------------
if (BIT(PIEP).b2) //
If ChannelA interrupt enabled
{
if (BIT(PIFP).b2) //
While ChannelA is interrupting
{
BIT(PTP).b3 = BIT(PTP).b3 ^ 0x01; //
debug
BIT(PIFP).b2 = CLEAR; //
Clear interrupt
}
}

// ChannelB IRQ
// ---------------------
if (BIT(PIEP).b7)
// If ChannelB is enabled
{
if (BIT(PIFP).b7)
// While ChannelB is interrupting
{
BIT(PTP).b6 = BIT(PTP).b6 ^ 0x01; //
debug
BIT(PIFP).b7 = CLEAR; //
Clear interrupt
}
}
}

Graham **********************************************************************
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Hi
> Hi
>
> I have a problem with interrupts on port P on a MC9S12DP256. I have two
> clock signals on P2 and P7 running at 19200 baud. I am interrupting on
the
> rising edge of each signal, I can run each of these independently with no
> problems. When I run both interrupts simultaneously I appear to lose
> interrupt flags for each signal. Below is my interrupt service routine
> which I have stripped to the basics of entering the routine clearing the
> flag and toggling a port pin for each channel. I think my problem is that
> the two clock signals occasionally coincide and only generate one
interrupt
> flag and the other gets lost somewhere or just ignored. My thinking at
the
> minute is to move one of the clock signals to another port but any other
> suggestions would be much appreciated.

There are 2 valid methods to clear interrupt flag. To clear Nth bit of
flags register FLGREG you
have to

LDAA #(1<<N)
STAA FLGREG

or

BCLR FLGREG,#~(1<<N) ; if N==4 read this line as BCLR FLGREG,#0xEF

And
BCLR FLGREG,#(1<<N) clears all flags except Nth
BCLR FLGREG,#0 clears all flags Now check what your compiler generates for following line.
> BIT(PIFP).b2 = CLEAR; //


Edward

> interrupt void PortP_ISR (void)
>
> {
>
> // ChannelA IRQ
> // ---------------------
> if (BIT(PIEP).b2) //
> If ChannelA interrupt enabled
> {
> if (BIT(PIFP).b2) //
> While ChannelA is interrupting
> {
> BIT(PTP).b3 = BIT(PTP).b3 ^ 0x01; //
> debug
> BIT(PIFP).b2 = CLEAR; //
> Clear interrupt
> }
> }
>
> // ChannelB IRQ
> // ---------------------
> if (BIT(PIEP).b7)
> // If ChannelB is enabled
> {
> if (BIT(PIFP).b7)
> // While ChannelB is interrupting
> {
> BIT(PTP).b6 = BIT(PTP).b6 ^ 0x01; //
> debug
> BIT(PIFP).b7 = CLEAR; //
> Clear interrupt
> }
> }
> }
>
> Graham > **********************************************************************
> This message contains confidential information and is intended only for
the individual named. If you are not the named addressee you should not
disseminate, distribute or copy this e-mail. Please notify the sender
immediately by e-mail if you have received this e-mail by mistake and delete
this e-mail from your system.
> Although BERU F1 SYSTEMS believe this e-mail and any attachments are free
of any virus or other defect which may affect a computer, it is the
responsibility of the recipient to ensure that it is virus free and BERU F1
SYSTEMS do not accept any responsibility for any loss or damage arising in
any way from its use.
> This footnote confirms that this email message has been swept by MAIL
Sweeper.
> **********************************************************************


Graham,
How is CLEAR defined?
Interrupt flag registers are cleared by writing a 1 to the bit to be cleared. If the bit in the flag register is set and a 1 is written to that bit, then the bit is cleared.

ed
--
At 03:58 PM 2/20/2004 +0000, you wrote:
>Hi
>
>I have a problem with interrupts on port P on a MC9S12DP256. I have two
>clock signals on P2 and P7 running at 19200 baud. I am interrupting on the
>rising edge of each signal, I can run each of these independently with no
>problems. When I run both interrupts simultaneously I appear to lose
>interrupt flags for each signal. Below is my interrupt service routine
>which I have stripped to the basics of entering the routine clearing the
>flag and toggling a port pin for each channel. I think my problem is that
>the two clock signals occasionally coincide and only generate one interrupt
>flag and the other gets lost somewhere or just ignored. My thinking at the
>minute is to move one of the clock signals to another port but any other
>suggestions would be much appreciated.
>
>interrupt void PortP_ISR (void)
>
>{
>
>// ChannelA IRQ
>// ---------------------
>if (BIT(PIEP).b2) //
>If ChannelA interrupt enabled
>{
> if (BIT(PIFP).b2) //
>While ChannelA is interrupting
> {
> BIT(PTP).b3 = BIT(PTP).b3 ^ 0x01; //
>debug
> BIT(PIFP).b2 = CLEAR; //
>Clear interrupt
> }
> }
>
> // ChannelB IRQ
> // ---------------------
> if (BIT(PIEP).b7)
>// If ChannelB is enabled
> {
> if (BIT(PIFP).b7)
>// While ChannelB is interrupting
> {
> BIT(PTP).b6 = BIT(PTP).b6 ^ 0x01; //
>debug
> BIT(PIFP).b7 = CLEAR; //
>Clear interrupt
> }
> }
>}
>
>Graham >**********************************************************************
>This message contains confidential information and is intended only for the individual named. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately by e-mail if you have received this e-mail by mistake and delete this e-mail from your system.
>Although BERU F1 SYSTEMS believe this e-mail and any attachments are free of any virus or other defect which may affect a computer, it is the responsibility of the recipient to ensure that it is virus free and BERU F1 SYSTEMS do not accept any responsibility for any loss or damage arising in any way from its use.
>This footnote confirms that this email message has been swept by MAIL Sweeper.
>********************************************************************** >
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