How much clock variance can BDM's tolerate?

Started by tonalbuilder2002 May 12, 2004
I'm working on a 9s12 project that requires an accurate 115200 baud
SCI. I want to run the 9s12 PLL at 22.1182 mHz, which gives a
perfect 115200 baud.

One possibility is to use a standard xtal frequency of 3.686 mHz, and
PLL it up to 22.118 mHz. But is 3.686 mHz too far off the mark for
my ComPod12-Pro BDM? All the BDM's I have looked at seem to require
1, 2, 4, or 8 mHz xtals...but what's the tolerance? I know the
ComPod12-Pro works fine with hc912's with 14.74 mHz oscillators, but
the 9s12 is a horse of a different color.

Other option is to use a 4.0mHz xtal with REFDV/SYNR set to 10/60,
which gives a tolerable 22.18 mHz. Has anybody observed any issues
when REFDV & SYNR are at large values? Does layout become super
critical or some such thing?

Would appreciate your thoughts. Maybe I need a custom xtal just
below 4 mHz.

P.S. Any recommends for 9s12-friendly xtals out of the Digi-Key
catalog?

Thanks, Bill T.




At 04:43 PM 5/12/2004, Bill T. wrote:
>I'm working on a 9s12 project that requires an accurate 115200 baud
>SCI. I want to run the 9s12 PLL at 22.1182 mHz, which gives a
>perfect 115200 baud.

I don't know what the specs of the transmission medium and the device on
the other end are, but it is likely that they won't notice an SCI clock
error less than 0.25%. They may well tolerate 1% or 2% error.

(Most SCI receiver implementations sample 16 times or less per ideal bit
time, and re-synchronize on the start pulse after no more than 11 bit
times. This suggests that they can tolerate an error of 1 sample time in
176 sample times. If this is true or your receiver, then an error between
the transmit clock and the receive clock of 1 in 200 or 0.5% won't
matter. Thus nominal frequency +/- 0.25% should be adequate.)

>One possibility is to use a standard xtal frequency of 3.686 mHz, and
>PLL it up to 22.118 mHz. But is 3.686 mHz too far off the mark for
>my ComPod12-Pro BDM? All the BDM's I have looked at seem to require
>1, 2, 4, or 8 mHz xtals...but what's the tolerance?

The tolerance experimentally is about +/- 10%. If you look at the Motorola
/ Freescale BDM documentation, the timing diagrams show the jitter effects
of the on-chip clock and the external BDM timing not being synchronized.

The good news is that the timing gets re-synchronized at the beginning of
each bit. The bad news is that a BDM emulator has to deduce that the clock
speed is not what it expects and go through some special gyrations to
figure out the correct speed.

Nohau's BDM and full emulators work with any frequency within the specs of
the HC-12 or HCS-12 parts.

With the Nohau BDM emulators you must tell the Nohau software ahead of time
what your external crystal or oscillator frequency is, and what PLL
parameters you want to use. The BDM emulator then checks BDM communication
and sets up the PLL.

If you have simple startup code that just sets the PLL to the desired
frequency, it doesn't notice that the part is already running at that
frequency.

Nohau's full emulators not only track the target speed changes, they
provide a full trace with timestamp through speed changes and resets,
making it clear what goes on when there are clock or speed problems.

>I know the ComPod12-Pro works fine with hc912's with 14.74 mHz
>oscillators, but the 9s12 is a horse of a different color.

As far as BDM communication is concerned there isn't much difference. If a
BDM system supported variable speed settings on the HC-12, if it supports
HCS-12 parts at all, it probably supports variable speed settings on them also.

>Other option is to use a 4.0mHz xtal with REFDV/SYNR set to 10/60,
>which gives a tolerable 22.18 mHz. Has anybody observed any issues
>when REFDV & SYNR are at large values? Does layout become super
>critical or some such thing?

Use the Motorola/Freescale PLL calculator to get the values for the PLL
filter on the XFC pin. It gives an estimate of the lock time, which will
be longer for bigger REFDV values, and also depends on the PLL filter.

Be aware that PLL lock time is variable. It is hard to get a good maximum
value, so something conservative like the estimated value being 1/5 or 1/10
of what you require is safe.

Depending on which silicon you are using, you may run into the errata of
the "lying lock bit". Under some conditions the PLL may indicate lock,
when in fact it is not locked.

The method that I recommend deals with the HC(S)-12 errata, and with
problems that I have experienced on other chips with PLLs. When testing
for PLL lock, make sure the lock is continuously indicated for several
periods of the phase detector. ( reference clock / ( REFDV+1 ) ). This
will not be fooled by most glitches in lock detector design.

While the crystal layout is critical, especially with the Colpitts
oscillator and higher frequency crystals, the PLL filter network on the XFC
pin is lower frequency and less critical. The result of noise coupled to
either circuit will cause some kind of clock jitter, so following the
Motorola/Freescale layout example is a good idea.

Steve Russell
Nohau emulators
*************************************************************************
Steve Russell mailto:
Senior Software Design Engineer http://www.nohau.com
Nohau Corporation phone: (408)866-1820 ext. 1873
51 East Campbell Avenue fax: (408)378-7869
Campbell, CA 95008
*************************************************************************


Hi Bill,

> I'm working on a 9s12 project that requires an accurate 115200 baud
> SCI. I want to run the 9s12 PLL at 22.1182 mHz, which gives a
> perfect 115200 baud.

most designs I've seen use 24 MHz and a divider of 13.
The resulting speed error is way below 1%. > One possibility is to use a standard xtal frequency of 3.686 mHz, and
> PLL it up to 22.118 mHz. But is 3.686 mHz too far off the mark for
> my ComPod12-Pro BDM? All the BDM's I have looked at seem to require
> 1, 2, 4, or 8 mHz xtals...but what's the tolerance? I know the
> ComPod12-Pro works fine with hc912's with 14.74 mHz oscillators, but
> the 9s12 is a horse of a different color.

ComPOD12/Pro tolerates deviations of up to +10% / -20% for both HC12 and
HCS12 targets, so 3.686Mhz should be no problem with 4MHz setting.

BTW, you are welcome to send such product related questions to
Elektronikladen support (support<a>elektronikladen.de) in case you
urgently need assistance.

good luck!
Oliver