DG256B PLL Resync

Started by peter_lingier June 7, 2004
Hello All,

I'm busy with a HCS12 DG256B. I have this PLL problem I would like
to discuss about.

I'm using the P&E programming and debugging tools.
When I step trough my code in debug mode, I put on a certain moment
the PLLSEL bit on one. My PLL is adjusted on 50MHz, based on an
oscilator clock of 4MHz.
In the Status Window of the debugger I see that the debugger
detected a change of the frequency (IO_DELAY_CNT changed to $0003).
But after this the data in RAM and stack changes at random and makes
my program to crash.

I made my program first for a DG128B and got everything working
nice. Now I want to adapt it to get it working for the both, but
I'm not succeeding due to the above problem.
Can anybody help. I know there are some errata in the 256, but I
don't see them having any influence on the problem. Maybe except
for errata MUCTS00436, but I think I got around this one by putting
in the configuration window the Re-sync to PLL Frequency Change to
YES. It resyncs though. If I put it on NO, I had the loss of sync
as described in the errata.

Greetings,

Peter