PLL doesn't run

Started by October 22, 2004
Hello !

I've problem with PLL on my board : it refuses to run.
On a other board, PLL runs OK.
The cpu core connecting (board) is the same on the two boards (obtained by
copy/paste)

I stay indefinitely in the "while" loop, that means LOCK bit never go to 1
state.
I tried other values for SYNR and REFDV registers, without any success.

Quartz is 12 Mhz, I try to run with PLL at 48 Mhz.

I verified power supply...

Has anyone meet this problem ?

Thanks.
Bests regards.

Joel.

Here is the code I use to select PLL

//----------------
#define SetBit(reg,masque) {reg |= masque;}
#define ClearBit(reg,masque) {reg &= ~masque;}
#define TestBit(reg,masque) (reg & masque)

// PLL Freq = Xtal * 2 * SYNR+1 / REFDV+1

void SGLE_SetSpeed_48 (void)
{ ClearBit (CLKSEL, PLLSEL); // select quartz
ClearBit (PLLCTL, PLLON); // stop PLL

SYNR = 19; // 12 Mhz * 2 * 20
REFDV = 9; // divided by 10
// equal 48 Mhz

SetBit (PLLCTL, PLLON); // start PLL

// I wait for PLL locked
while (! TestBit(CRGFLG, LOCK))
;

SetBit (CLKSEL, PLLSEL); // select PLL
}



Hello,

You want PLLHMHz and bus clock$MHz?

In this case with quartz at 12MHz it is SYNR=3 REFDV=1

If you want bus clock at 48MHz, i don't think that it is possible (f bus max%Mhz)

Regards
----- Original Message -----
From:
To:
Sent: Friday, October 22, 2004 8:38 AM
Subject: [68HC12] PLL doesn't run Hello !

I've problem with PLL on my board : it refuses to run.
On a other board, PLL runs OK.
The cpu core connecting (board) is the same on the two boards (obtained by
copy/paste)

I stay indefinitely in the "while" loop, that means LOCK bit never go to 1
state.
I tried other values for SYNR and REFDV registers, without any success.

Quartz is 12 Mhz, I try to run with PLL at 48 Mhz.

I verified power supply...

Has anyone meet this problem ?

Thanks.
Bests regards.

Joel.

Here is the code I use to select PLL

//----------------
#define SetBit(reg,masque) {reg |= masque;}
#define ClearBit(reg,masque) {reg &= ~masque;}
#define TestBit(reg,masque) (reg & masque)

// PLL Freq = Xtal * 2 * SYNR+1 / REFDV+1

void SGLE_SetSpeed_48 (void)
{ ClearBit (CLKSEL, PLLSEL); // select quartz
ClearBit (PLLCTL, PLLON); // stop PLL

SYNR = 19; // 12 Mhz * 2 * 20
REFDV = 9; // divided by 10
// equal 48 Mhz

SetBit (PLLCTL, PLLON); // start PLL

// I wait for PLL locked
while (! TestBit(CRGFLG, LOCK))
;

SetBit (CLKSEL, PLLSEL); // select PLL
}
------
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I'm using an 8Mhz oscillator and using the PLL to up
that to 48Mhz. Here is how mine turns on. You will
need to use different SYNR & REFDV values.

I recommend going to Motorolas website and downloading
the PLL circuit calculator. It calculates the caps &
resistor that you need to get a stable PLL circuit.
You can change the stability, which changes the amount
of time that the PLL circuit needs to lock, by
changing the caps and resistor. It is possible the
PLL circuit you are using is not stable with the PLL
speed you are trying to achieve. SYNR = 2;
REFDV = 0;
PLLCTL |= 0x60;
while(!(CRGFLG & 0x08)) {}
CLKSEL |= 0x80;

What everything does.

PLLCTL |= 0x60; Enables PLL circuit & Automatic
Bandwith Control

Then I spin on the while() until the PLL stabalizes.

CLKSEL |= 0x80; Sets system clock to PLL That should get you up and running. Jason M. Liszewski

--- wrote:

> Hello !
>
> I've problem with PLL on my board : it refuses to
> run.
> On a other board, PLL runs OK.
> The cpu core connecting (board) is the same on the
> two boards (obtained by
> copy/paste)
>
> I stay indefinitely in the "while" loop, that means
> LOCK bit never go to 1
> state.
> I tried other values for SYNR and REFDV registers,
> without any success.
>
> Quartz is 12 Mhz, I try to run with PLL at 48 Mhz.
>
> I verified power supply...
>
> Has anyone meet this problem ?
>
> Thanks.
> Bests regards.
>
> Joel.
>
> Here is the code I use to select PLL
//----------------
> #define SetBit(reg,masque) {reg |= masque;}
> #define ClearBit(reg,masque) {reg &= ~masque;}
> #define TestBit(reg,masque) (reg & masque)
>
> // PLL Freq = Xtal * 2 * SYNR+1 / REFDV+1
>
> void SGLE_SetSpeed_48 (void)
> { ClearBit (CLKSEL, PLLSEL); // select quartz
> ClearBit (PLLCTL, PLLON); // stop PLL
>
> SYNR = 19; // 12 Mhz * 2 * 20
> REFDV = 9; // divided by 10
> // equal 48 Mhz
>
> SetBit (PLLCTL, PLLON); // start PLL
>
> // I wait for PLL locked
> while (! TestBit(CRGFLG, LOCK))
> ;
>
> SetBit (CLKSEL, PLLSEL); // select PLL
> } >

_______________________________



Thank you, Pascal and Jason.

I see I use the same code as you.
Except for the value in SYNR and REFDV.
I don't remember why I took that kind of value SYNR and REFDV=9.
SYNR=3 and REFDV=0 wil give the same result.

So, I think the problem is may be in hardware.

Nice week-end !