Problem with I2C Bus

Started by ymliao December 3, 2004

Hi Everyone!

I am using an evaluation board for the MC9S12E128 micro from
Technological Art. I've been trying to get the micro to talk to a RTC
from ST (M41T81) via I2C bus but noticed the following problems...

Problem 1)
The bus frequency is 24MHz. The I2C bus frequency divider is set to
be 240 (by writing 0x1F to IBFD), which should give a SCL of 100kHz.
However, from scope, the actual SCL frequency is about 71kHz.

Problem 2)
I can write to the slave device. But there is still a small problem
with the write operation. On the scope, I can see that the slave acks
to the master by pulling the SDA line low. However, the last bit RXAK
(received acknowledge) of IBSR (I2C bus status register) is 1, which
means the master has not received acknowledgement from the slave.
This contradicts what's been displayed on the scope. And it affects
the way I implement my write routine (or interrupt routine) as I have
to assume that the slave has acked to every byte without checking
(even if I check, RXAK in IBSR is always 1 anyway...). So this is a
problem as I have no way to know whether the slave has really acks or
not.

Problem 3)
For reading from a slave there seems to be more problem. Here is how
I perform a read operation:
1) Send start signal
2) Send out slave's address with LSB set to write
3) Send out the register I want to read
4) Send restart signal
5) Sent out slave's address with LSB set to read
6) Change master to receive mode (from transmit mode)
7) Dummy read IBDR (IIC bus data i/o register)
8) Read IBDR again

If I perform the above steps all at once, from scope, I can see steps
1 to 3 are done correctly with slave's acknowledement. But there is
problem after the restart signal. The SDA bus is stucked low for some
reason.

But if I use the "single step" function in the debugger, I can see
the steps 4 to 6 being done properly. As for steps 7) and 8),
sometimes I can see the correctly value displayed on the scope but
the IBDR has something totally differently such as 0xFF. The rest of
times I don't even get the properly waveform on the scope.

Thanks for reading this long post. Any help/suggestion is greatly
appreciated!

Amy




There is some discussion of the IIC bus in the achives of this Forumn.

Andrew Lohmann AIIE
Design Engineer

PLEASE NOTE NEW EMAIL ADDRESS IS: Bellingham + Stanley Ltd.
Longfield Road, Tunbridge Wells, Kent, TN2 3EY, England.
Tel: +44 (0) 1892 500400
Fax: +44 (0) 1892 543115
Website: www.bs-ltd.com
ymliao wrote:

>
> Hi Everyone!
>
> I am using an evaluation board for the MC9S12E128 micro from
> Technological Art. I've been trying to get the micro to talk to a RTC
> from ST (M41T81) via I2C bus but noticed the following problems...
>
> Problem 1)
> The bus frequency is 24MHz. The I2C bus frequency divider is set to
> be 240 (by writing 0x1F to IBFD), which should give a SCL of 100kHz.
> However, from scope, the actual SCL frequency is about 71kHz.
>
> Problem 2)
> I can write to the slave device. But there is still a small problem
> with the write operation. On the scope, I can see that the slave acks
> to the master by pulling the SDA line low. However, the last bit RXAK
> (received acknowledge) of IBSR (I2C bus status register) is 1, which
> means the master has not received acknowledgement from the slave.
> This contradicts what's been displayed on the scope. And it affects
> the way I implement my write routine (or interrupt routine) as I have
> to assume that the slave has acked to every byte without checking
> (even if I check, RXAK in IBSR is always 1 anyway...). So this is a
> problem as I have no way to know whether the slave has really acks or
> not.
>
> Problem 3)
> For reading from a slave there seems to be more problem. Here is how
> I perform a read operation:
> 1) Send start signal
> 2) Send out slave's address with LSB set to write
> 3) Send out the register I want to read
> 4) Send restart signal
> 5) Sent out slave's address with LSB set to read
> 6) Change master to receive mode (from transmit mode)
> 7) Dummy read IBDR (IIC bus data i/o register)
> 8) Read IBDR again
>
> If I perform the above steps all at once, from scope, I can see steps
> 1 to 3 are done correctly with slave's acknowledement. But there is
> problem after the restart signal. The SDA bus is stucked low for some
> reason.
>
> But if I use the "single step" function in the debugger, I can see
> the steps 4 to 6 being done properly. As for steps 7) and 8),
> sometimes I can see the correctly value displayed on the scope but
> the IBDR has something totally differently such as 0xFF. The rest of
> times I don't even get the properly waveform on the scope.
>
> Thanks for reading this long post. Any help/suggestion is greatly
> appreciated!
>
> Amy >
>
> *
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