TCM vs. internal SRAM

Hi all,

I was curious if I could increase my performance using TCMs.
Currently, I am loading my interrupt handler code to internal fast SRAM.
Would it make sense if use part of this memory as I-TCM and load the irq
handlers to this location?
Regards,
Bekir Start a New Thread

ICLI, Bekir (EXT) schrieb:

> I was curious if I could increase my performance using TCMs.
> Currently, I am loading my interrupt handler code to internal fast SRAM.
> Would it make sense if use part of this memory as I-TCM and load the irq
> handlers to this location?

Yes. TCM runs at CPU speed, SRAM at AHB speed (1/2 of CPU speed).

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Hi Bekir

> #define ITCM_BASE 0x100000 /* In memory map, I-TCM is located at the second MB, but I have a feeling like what I am doing here might not be correct */
> #define ITCM_SIZE (0x5 << 2) /* 16KB */
> #define ITCM_ENABLE 0x1
> #define ITCM_PATTERN (ITCM_BASE | ITCM_SIZE | ITCM_ENABLE)
>
> MRC p15, 0, r1, c9, c1, 1
> ORR r1, r1, #ITCM_PATTERN
> MCR p15, 0, r1, c9, c1, 1
>
> And I am copying the IRQ handler code not the the internal SRAM, but to the second MB.
> But it stops at the first interrupt.
> Should I take another measure to enable TCM??

Yes. You need to enable it also in the controller but I do not know the
register by heart.

All I remember is that the order was important.

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42Bastian

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Hi Bastian,

I guess I am missing something, while enabling the I-TCM.
I am doing the following:

#define ITCM_BASE 0x100000 /* In memory map, I-TCM is located at the second MB, but I have a feeling like what I am doing here might not be correct */
#define ITCM_SIZE (0x5 << 2) /* 16KB */
#define ITCM_ENABLE 0x1
#define ITCM_PATTERN (ITCM_BASE | ITCM_SIZE | ITCM_ENABLE)

MRC p15, 0, r1, c9, c1, 1
ORR r1, r1, #ITCM_PATTERN
MCR p15, 0, r1, c9, c1, 1

And I am copying the IRQ handler code not the the internal SRAM, but to the second MB.
But it stops at the first interrupt.
Should I take another measure to enable TCM??

Mit freundlichem Gru/ Best regards

Bekir ICLI

Siemens AG
Automation and Drives, Automation and Drives, A&D SC IC RD4
Tel. : +49 (721) 595-3280
mailto:b...@siemens.com
http://www.siemens.com/automation

Siemens Aktiengesellschaft: Chairman of the Supervisory Board: Gerhard Cromme
Managing Board: Peter Loescher, Chairman, President and Chief Executive Officer;
Wolfgang Dehen, Heinrich Hiesinger, Joe Kaeser, Erich R. Reinhardt, Hermann Requardt,
Siegfried Russwurm, Peter Y. Solmssen
Registered offices: Berlin and Munich;
Commercial registries: Berlin Charlottenburg, HRB 12300, Munich, HRB 6684
WEEE-Reg.-No. DE 23691322

-----Ursprgliche Nachricht-----
Von: A... [mailto:A...] Im Auftrag von 42Bastian
Gesendet: Dienstag, 18. Mz 2008 15:16
An: A...
Betreff: Re: [AT91SAM] TCM vs. internal SRAM

ICLI, Bekir (EXT) schrieb:

> I was curious if I could increase my performance using TCMs.
> Currently, I am loading my interrupt handler code to internal fast SRAM.
> Would it make sense if use part of this memory as I-TCM and load the irq
> handlers to this location?

Yes. TCM runs at CPU speed, SRAM at AHB speed (1/2 of CPU speed).

--
42Bastian

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ICLI, Bekir (EXT) schrieb:
> Thanks for the answers Bastian.
>
> I hope there is someone who can explain this to me.
> No matter when I read the TCM status from c0 (after or before enabling), it says always 0.
> There are definitely somethings points I am missing here.

Here the code which works for DTCM:

@ set the matrix register
mov r0, #0x50 @ DTCM = 16 Kbytes, ITCM = 0 Kbytes
ldr r1, =0xFFFFEE24
str r0, [r1]
@ Nop to prevent pipeline stall! (PGe/ Schick)
@nop
@ Better: instead of nop use a branch to completly flush the pipeline
b dummy_dtcm
dummy_dtcm:
@ set the size end enable it in the coprocessor
ldr r0, =0x31000015
mcr p15, 0, r0, c9, c1, 0

But I am not sure about the b dummy_dtcm maybe a bx is better.
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Hi Bastian,

This takes me one step closer to the correct answer but not yet.
Now I can read from c0 that I-TCM is enabled.
I can see in c9 that 16K I-TCM is enabled.
But I guess I still don't have the insight to this.
What I do is:
1- I wrote a dummy function, and placed it in the linker script to the sdram, with the virtual address of 0x00100000.(This address is shown as the ITCM start address).
2- Copied the dummy function from sdram to the address 0x00100000.
2- Enabled the ITCM as 16K in matrix tcm configuration register.
3- Enabled the ITCM in coprocessor register as 16K with base address 0x00100000. (This is where I am not quite sure)
4- Called the function.

And the execution stops as soon as I call the dummy function. Giving no exception or anything..

Mit freundlichem Gru/ Best regards

Bekir ICLI

Siemens AG
Automation and Drives, Automation and Drives, A&D SC IC RD4
Tel. : +49 (721) 595-3280
mailto:b...@siemens.com
http://www.siemens.com/automation

Siemens Aktiengesellschaft: Chairman of the Supervisory Board: Gerhard Cromme
Managing Board: Peter Loescher, Chairman, President and Chief Executive Officer;
Wolfgang Dehen, Heinrich Hiesinger, Joe Kaeser, Erich R. Reinhardt, Hermann Requardt,
Siegfried Russwurm, Peter Y. Solmssen
Registered offices: Berlin and Munich;
Commercial registries: Berlin Charlottenburg, HRB 12300, Munich, HRB 6684
WEEE-Reg.-No. DE 23691322

-----Ursprgliche Nachricht-----
Von: A... [mailto:A...] Im Auftrag von 42Bastian
Gesendet: Mittwoch, 19. Mz 2008 07:22
An: A...
Betreff: Re: AW: AW: [AT91SAM] TCM vs. internal SRAM

ICLI, Bekir (EXT) schrieb:
> Thanks for the answers Bastian.
>
> I hope there is someone who can explain this to me.
> No matter when I read the TCM status from c0 (after or before enabling), it says always 0.
> There are definitely somethings points I am missing here.

Here the code which works for DTCM:

@ set the matrix register
mov r0, #0x50 @ DTCM = 16 Kbytes, ITCM = 0 Kbytes
ldr r1, =0xFFFFEE24
str r0, [r1]
@ Nop to prevent pipeline stall! (PGe/ Schick)
@nop
@ Better: instead of nop use a branch to completly flush the pipeline
b dummy_dtcm
dummy_dtcm:
@ set the size end enable it in the coprocessor
ldr r0, =0x31000015
mcr p15, 0, r0, c9, c1, 0

But I am not sure about the b dummy_dtcm maybe a bx is better.
--
42Bastian

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Thanks for the answers Bastian.

I hope there is someone who can explain this to me.
No matter when I read the TCM status from c0 (after or before enabling), it says always 0.
There are definitely somethings points I am missing here.
Mit freundlichem Gru/ Best regards

Bekir ICLI

-----Ursprgliche Nachricht-----
Von: A... [mailto:A...] Im Auftrag von 42Bastian
Gesendet: Dienstag, 18. Mz 2008 16:27
An: A...
Betreff: Re: AW: [AT91SAM] TCM vs. internal SRAM

Hi Bekir

> #define ITCM_BASE 0x100000 /* In memory map, I-TCM is located at the second MB, but I have a feeling like what I am doing here might not be correct */
> #define ITCM_SIZE (0x5 << 2) /* 16KB */
> #define ITCM_ENABLE 0x1
> #define ITCM_PATTERN (ITCM_BASE | ITCM_SIZE | ITCM_ENABLE)
>
> MRC p15, 0, r1, c9, c1, 1
> ORR r1, r1, #ITCM_PATTERN
> MCR p15, 0, r1, c9, c1, 1
>
> And I am copying the IRQ handler code not the the internal SRAM, but to the second MB.
> But it stops at the first interrupt.
> Should I take another measure to enable TCM??

Yes. You need to enable it also in the controller but I do not know the
register by heart.

All I remember is that the order was important.

--
42Bastian

Note: SPAM-only account, direct mail to bs42@...

Start a New Thread