CAN Interrupt

Hi all,

I'm using TMS320F28335 eZDSP.
I program a code that use CANa to receive messages in Mailbox31 (0-15TX, 16-31RX). also I handle with the DSP/BIOS interrupt for the CANa module (PIEACK.Group9.6 - ECAN1IntA).
I "build" a little CAN net: canAnalyzer --- eZDSP ----- CANKing

my problem is: I sending a NMT message to the net and I've got the interrupt, but when i sending again I don't get any interrupt at all why?

I'm using the defualt TI setting for the CAN module and I add this code also for setting the CANa module.

The code is:
void IniteCANModule()
{

// eCAN control registers require read/write access using 32-bits. Thus we
// will create a set of shadow registers for this example. These shadow
// registers will be used to make sure the access is 32-bits and not 16.
struct ECAN_REGS ECanaShadow;

InitECanGpio();//from TI examples
InitECan();//from TI examples
/* Configure MSGID */
ECanaMboxes.MBOX31.MSGID.all = 0;

/* Configure Acceptance Mask */
ECanaLAMRegs.LAM31.all = 0x1FFFFFFF;//Don't care

/* Configure Mailboxes */
// Configure Mailboxes 0-15 as Tx, 16-31 as Rx
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.all = 0xFFFF0000;//Mailbox31 defined as a receive mailbox
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Configure Mailbox protected */
ECanaShadow.CANOPC.all = ECanaRegs.CANOPC.all;
ECanaShadow.CANOPC.bit.OPC31 = 0;//the message can be overwritten
ECanaRegs.CANOPC.all = ECanaShadow.CANOPC.all;

ECanaMboxes.MBOX31.MSGCTRL.bit.DLC = 8;

/* Enable Mailboxes */
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.all = 0xFFFFFFFF;//Enable all Mailboxes
ECanaRegs.CANME.all = ECanaShadow.CANME.all;

EALLOW;

//configuration for interrupt handling
ECanaRegs.CANMIM.all = 0xFFFFFFFF; //16-31 mailboxes interrupt are enabled
ECanaRegs.CANMIL.all = 0xFFFFFFFF; //mailbox interrupt level (mapped to eCAN1INT line lower priority CPU line 0)
ECanaRegs.CANGIM.all = 0x00002E06;

PieCtrlRegs.PIEIER9.bit.INTx6 = 1; // Enable INTx.6 of INT9 (eCAN1INT)

EDIS; // Disable EALLOW protected register access

}

Please help me with this interrupt issue.
Thanks.


Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467 Start a New Thread

You are getting the interrupt at first time only,As Per my knowledge every ISR must end with a acknowledge to the CPU ie we have a responsibility to set the appropriate bit in PIEACK register,Check once did u set that bit in ISR or not.
Regards..

Srinivas
Hi all,
>
>I'm using TMS320F28335 eZDSP.
>I program a code that use CANa to receive messages in Mailbox31 (0-15TX, 16-31RX). also I handle with the DSP/BIOS interrupt for the CANa module (PIEACK.Group9.6 - ECAN1IntA).
>I "build" a little CAN net: canAnalyzer --- eZDSP ----- CANKing
>
>my problem is: I sending a NMT message to the net and I've got the interrupt, but when i sending again I don't get any interrupt at all why?
>
>I'm using the defualt TI setting for the CAN module and I add this code also for setting the CANa module.
>
>The code is:
>void IniteCANModule()
>{
>
>// eCAN control registers require read/write access using 32-bits. Thus we
>// will create a set of shadow registers for this example. These shadow
>// registers will be used to make sure the access is 32-bits and not 16.
> struct ECAN_REGS ECanaShadow;
>
> InitECanGpio();//from TI examples
> InitECan();//from TI examples
> /* Configure MSGID */
> ECanaMboxes.MBOX31.MSGID.all = 0;
>
> /* Configure Acceptance Mask */
> ECanaLAMRegs.LAM31.all = 0x1FFFFFFF;//Don't care
>
> /* Configure Mailboxes */
> // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
> ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
> ECanaShadow.CANMD.all = 0xFFFF0000;//Mailbox31 defined as a receive mailbox
> ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
>
> /* Configure Mailbox protected */
> ECanaShadow.CANOPC.all = ECanaRegs.CANOPC.all;
> ECanaShadow.CANOPC.bit.OPC31 = 0;//the message can be overwritten
> ECanaRegs.CANOPC.all = ECanaShadow.CANOPC.all;
>
> ECanaMboxes.MBOX31.MSGCTRL.bit.DLC = 8;
>
> /* Enable Mailboxes */
> ECanaShadow.CANME.all = ECanaRegs.CANME.all;
> ECanaShadow.CANME.all = 0xFFFFFFFF;//Enable all Mailboxes
> ECanaRegs.CANME.all = ECanaShadow.CANME.all;
>
> EALLOW;
>
> //configuration for interrupt handling
> ECanaRegs.CANMIM.all = 0xFFFFFFFF; //16-31 mailboxes interrupt are enabled
> ECanaRegs.CANMIL.all = 0xFFFFFFFF; //mailbox interrupt level (mapped to eCAN1INT line lower priority CPU line 0)
> ECanaRegs.CANGIM.all = 0x00002E06;
>
> PieCtrlRegs.PIEIER9.bit.INTx6 = 1; // Enable INTx.6 of INT9 (eCAN1INT)
>
> EDIS; // Disable EALLOW protected register access
>
>}
>
>Please help me with this interrupt issue.
>Thanks.
>


Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467 Start a New Thread

Hi all,

I solved this probelm.
for each can interrupt reset DSP CAN registers is demand.
that why i add to my code:

EALLOW;
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
EDIS;

in the CAN_ISR routine.

Hi all,
>
>I'm using TMS320F28335 eZDSP.
>I program a code that use CANa to receive messages in Mailbox31 (0-15TX, 16-31RX). also I handle with the DSP/BIOS interrupt for the CANa module (PIEACK.Group9.6 - ECAN1IntA).
>I "build" a little CAN net: canAnalyzer --- eZDSP ----- CANKing
>
>my problem is: I sending a NMT message to the net and I've got the interrupt, but when i sending again I don't get any interrupt at all why?
>
>I'm using the defualt TI setting for the CAN module and I add this code also for setting the CANa module.
>
>The code is:
>void IniteCANModule()
>{
>
>// eCAN control registers require read/write access using 32-bits. Thus we
>// will create a set of shadow registers for this example. These shadow
>// registers will be used to make sure the access is 32-bits and not 16.
> struct ECAN_REGS ECanaShadow;
>
> InitECanGpio();//from TI examples
> InitECan();//from TI examples
> /* Configure MSGID */
> ECanaMboxes.MBOX31.MSGID.all = 0;
>
> /* Configure Acceptance Mask */
> ECanaLAMRegs.LAM31.all = 0x1FFFFFFF;//Don't care
>
> /* Configure Mailboxes */
> // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
> ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
> ECanaShadow.CANMD.all = 0xFFFF0000;//Mailbox31 defined as a receive mailbox
> ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
>
> /* Configure Mailbox protected */
> ECanaShadow.CANOPC.all = ECanaRegs.CANOPC.all;
> ECanaShadow.CANOPC.bit.OPC31 = 0;//the message can be overwritten
> ECanaRegs.CANOPC.all = ECanaShadow.CANOPC.all;
>
> ECanaMboxes.MBOX31.MSGCTRL.bit.DLC = 8;
>
> /* Enable Mailboxes */
> ECanaShadow.CANME.all = ECanaRegs.CANME.all;
> ECanaShadow.CANME.all = 0xFFFFFFFF;//Enable all Mailboxes
> ECanaRegs.CANME.all = ECanaShadow.CANME.all;
>
> EALLOW;
>
> //configuration for interrupt handling
> ECanaRegs.CANMIM.all = 0xFFFFFFFF; //16-31 mailboxes interrupt are enabled
> ECanaRegs.CANMIL.all = 0xFFFFFFFF; //mailbox interrupt level (mapped to eCAN1INT line lower priority CPU line 0)
> ECanaRegs.CANGIM.all = 0x00002E06;
>
> PieCtrlRegs.PIEIER9.bit.INTx6 = 1; // Enable INTx.6 of INT9 (eCAN1INT)
>
> EDIS; // Disable EALLOW protected register access
>
>}
>
>Please help me with this interrupt issue.
>Thanks.
>


Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467 Start a New Thread