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eCAN Error

Started by AminRezaie June 8, 2009
Hi
I've some experience in using 2812 peripheral but not on ecan.
now i want use can bus to connect to the motor driver to make some change onto configuration or set point. but i have no ack. in can bus.
I set TRS0 and wait for TA0 to be set but after 180 time read and check CANTA reg CANEs register set some flag like(SMA, EW and EP), and repeat.
i'm so confused.
my code is :

void main(void)
{
int count = 0;
struct ECAN_REGS ECanaShadow;
InitSysCtrl();
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
/* Configure eCAN pins for CAN operation using GPIO regs*/
EALLOW;
GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
// eCAN control registers require 32-bit access.
// If you want to write to a single bit, the compiler may break this
// access into a 16-bit access. One solution, that is presented here,
// is to use a shadow register to force the 32-bit access.

// Read the entire register into a shadow register. This access
// will be 32-bits. Change the desired bit and copy the value back
// to the eCAN register with a 32-bit write.
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
EALLOW;
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
EALLOW;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
//ECanaShadow.CANMC.bit.SCB = 1; // eCAN mode
ECanaShadow.CANMC.bit.SCB = 0; // SCC mode
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register may come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
/* Clear all TAn bits */
ECanaRegs.CANTA.all= 0xFFFFFFFF;
/* Clear all RMPn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF;
/* Clear all interrupt flag bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters */
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
if(ECanaShadow.CANES.bit.CCE != 1 )
{
// Wait for CCE bit to be set..
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
}
/*
// Configure bit timing parameters
// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
*/
EALLOW;
ECanaShadow.CANBTC.all = 0;
// ECanaShadow.CANBTC.bit.BRPREG = 15;// 1 Mbps @ 100 MHz SYSCLKOUT
// ECanaShadow.CANBTC.bit.BRPREG = 300;// 50 Kbps @ 100 MHz SYSCLKOUT
ECanaShadow.CANBTC.bit.BRPREG = 30;// 500 Kbps @ 100 MHz SYSCLKOUT
ECanaShadow.CANBTC.bit.TSEG1REG = 6;
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
/*
use LAM for SCC mode
The table below shows how BRP(reg) field must be changed to achieve different bit
rates with a BT of 10, for a 80% SP:
-------------------------
BT = 10, TSEG1(reg) = 6, TSEG2(reg) = 1, Sampling Point = 80%
-------------------------
1 Mbps : BRP(reg)+1 = 15 : CAN clock = 10 MHz
500 kbps : BRP(reg)+1 = 30 : CAN clock = 5 MHz
250 kbps : BRP(reg)+1 = 60 : CAN clock = 2.5 MHz
125 kbps : BRP(reg)+1 = 120: CAN clock = 1.25 MHz
100 kbps : BRP(reg)+1 = 150 : CAN clock = 1 MHz
50 kbps : BRP(reg)+1 = 300 : CAN clock = 0.5 MHz
*/
EALLOW;
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaShadow.CANMC.bit.DBO = 0; // dat out by MSB
//ECanaShadow.CANMC.bit.DBO = 1; //data out by LSB
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/*
// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
*/

//ECanaShadow.CANTRR.all = 0x00000000;
ECanaRegs.CANTRR.all = 0x00000000;
do
{
ECanaShadow.CANTRS.all = ECanaRegs.CANTRS.all;

}while(ECanaShadow.CANTRS.bit.TRS0 != 0);
/* Disable all Mailboxes */
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
EALLOW;
ECanaRegs.CANME.all = 0;// Required before writing the MSGIDs
ECanaMboxes.MBOX0.MSGID.bit.STDMSGID = 1541;
ECanaMboxes.MBOX0.MSGID.bit.AAM = 0;
ECanaMboxes.MBOX0.MSGID.bit.AME = 0;
ECanaMboxes.MBOX0.MSGID.bit.IDE = 0;
ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX0.MDH.all = 0x40c25f00;
ECanaMboxes.MBOX0.MDL.all = 0x00000000;
//ECanaMboxes.MBOX0.MDL.all = 0x40c25f00;
//ECanaMboxes.MBOX0.MDH.all = 0x00000000;

// Configure Mailboxes 0-15 as Tx, 16-31 as Rx
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanaRegs.CANMD.all = 0xFFFFFFFE;
// Enable all Mailboxes */
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanaRegs.CANME.all = 0xFFFFFFFF;
// Configure the eCAN for self test mode
// Enable the enhanced features of the eCAN.
EALLOW;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
// ECanaShadow.CANMC.bit.STM = 1; // Configure CAN for self-test mode
ECanaShadow.CANMC.bit.STM = 0; // Configure CAN for normal mode
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

// Configure Mailboxes 0-15 as Tx, 16-31 as Rx
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanaRegs.CANMD.all = 0xFFFF0000;
// Enable all Mailboxes */
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
ECanaRegs.CANME.all = 0xFFFFFFFF;

while(1)
{
// ECanaRegs.CANTRS.all = 0x00000001; // Set TRS for all transmit mailboxes
ECanaRegs.CANTRS.bit.TRS0 = 1; // Set TRS0 for transmit mailboxe 0
do
{
if(ECanaRegs.CANES.all != 0)
asm("nop");
ECanaShadow.CANTA.all = ECanaRegs.CANTA.all;
count++;
}while(ECanaShadow.CANTA.bit.TA0 != 1); // Wait for all TAn bits to be set..
ECanaRegs.CANTA.bit.TA0 = 1; // Clear all TAn
}
}



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