free cpu 8051 verilog code

http://bknpk.no-ip.biz/cpu_8051_ver/top.html

#

Stable Design: The design is translated from a VHDL dalton project
http://www.cs.ucr.edu/~dalton/i8051/i8051syn.
#

Small Design: Consumes only 324 Flip-Flops: map report
#

Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report

Cross posted to comp.arch.fpga, as this is an intersting resource.

Pinhas wrote:

> http://bknpk.no-ip.biz/cpu_8051_ver/top.html
> 
> #
> 
> Stable Design: The design is translated from a VHDL dalton project
> http://www.cs.ucr.edu/~dalton/i8051/i8051syn.
> #
> 
> Small Design: Consumes only 324 Flip-Flops: map report

More map report details, from the link :
Target Device : xc4vlx25
Number of Slice Flip Flops: 324 out of 21,504 1%
Total Number 4 input LUTs: 2,423 out of 21,504 11%

> #
> 
> Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report

-jg

Jim Granville wrote:
>>
>> Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
> 

I don't want to nitpick. It looks like a nice and (maybe more important) 
little project.

But on the web site I see the following performance figures:

I8051_ALU:

   Critical Path Length (ns): 178
   Maximum Clock Speed (MHz): 5.63
	
I have to admit that I'm a FPGA noob, but I think that part deserves 
some optimization.

Nils

"Nils" <n.pipenbrinck@cubic.org> wrote in message 
news:6lnd94Fda23nU1@mid.uni-berlin.de...
> Jim Granville wrote:
>>>
>>> Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
>>
>
> I don't want to nitpick. It looks like a nice and (maybe more important) 
> little project.
>
> But on the web site I see the following performance figures:
>
> I8051_ALU:
>
>   Critical Path Length (ns): 178
>   Maximum Clock Speed (MHz): 5.63
>
> I have to admit that I'm a FPGA noob, but I think that part deserves some 
> optimization.
>
> Nils

Without reading TFA, I agree, I laughed where it says it's a small design 
because it only uses 324 FFs, and yet it uses 10 times as many LUTs!

Cheers, Syms.

"Nils" <n.pipenbrinck@cubic.org> wrote in message
news:6lnd94Fda23nU1@mid.uni-berlin.de...
> Jim Granville wrote:
> >>
> >> Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
> >
>
> I don't want to nitpick. It looks like a nice and (maybe more important)
> little project.
>
> But on the web site I see the following performance figures:
>
> I8051_ALU:
>
>    Critical Path Length (ns): 178
>    Maximum Clock Speed (MHz): 5.63
>
> I have to admit that I'm a FPGA noob, but I think that part deserves
> some optimization.

And some work too....

Quote:
Limitations:
  This implementation is not cycle/timing compatible.
  Interrupt handling is not currently implemented.
  Peripheral devices are not currently implemented.

Meindert

On 16 =D7=90=D7=95=D7=A7=D7=98=D7=95=D7=91=D7=A8, 08:27, "Meindert Sprang"
<m...@NOJUNKcustomORSPAMware.nl> wrote:
> "Nils" <n.pipenbri...@cubic.org> wrote in message
>
> news:6lnd94Fda23nU1@mid.uni-berlin.de...
>
>
>
> > Jim Granville wrote:
>
> > >> Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
>
> > I don't want to nitpick. It looks like a nice and (maybe more important=
)
> > little project.
>
> > But on the web site I see the following performance figures:
>
> > I8051_ALU:
>
> > =C2=A0 =C2=A0Critical Path Length (ns): 178
> > =C2=A0 =C2=A0Maximum Clock Speed (MHz): 5.63
>
> > I have to admit that I'm a FPGA noob, but I think that part deserves
> > some optimization.
>
> And some work too....
>
> Quote:
> Limitations:
> =C2=A0 This implementation is not cycle/timing compatible.
> =C2=A0 Interrupt handling is not currently implemented.
> =C2=A0 Peripheral devices are not currently implemented.
>
> Meindert

As far as I remeber this is a multicycle path. But I'll double check.

"Pinhas" <bknpk@hotmail.com> wrote in message 
news:4a8728cf-85d9-4cf8-90e2-f749e2cc4e0d@p31g2000prf.googlegroups.com...
> http://bknpk.no-ip.biz/cpu_8051_ver/top.html
> Stable Design: The design is translated from a VHDL dalton project
> http://www.cs.ucr.edu/~dalton/i8051/i8051syn.
> Small Design: Consumes only 324 Flip-Flops: map report
> Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report

But I wonder why anyone would want to put such an archaic computing machine 
in an FPGA (except for academic purposes).  There are much better cores 
available.

JJS

"John Speth" <johnspeth@yahoo.com> wrote in message 
news:gd7ken$9ph$1@aioe.org...
> "Pinhas" <bknpk@hotmail.com> wrote in message 
> news:4a8728cf-85d9-4cf8-90e2-f749e2cc4e0d@p31g2000prf.googlegroups.com...
>> http://bknpk.no-ip.biz/cpu_8051_ver/top.html
>> Stable Design: The design is translated from a VHDL dalton project
>> http://www.cs.ucr.edu/~dalton/i8051/i8051syn.
>> Small Design: Consumes only 324 Flip-Flops: map report
>> Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report
>
> But I wonder why anyone would want to put such an archaic computing 
> machine in an FPGA (except for academic purposes).  There are much better 
> cores available.

https://admin.na3.acrobat.com/_a803410391/p86518030/

Hans
www.ht-lab.com



>
> JJS
>
>