C-to-Verilog for embedded designs

Started by Nadav Rotem December 14, 2008

My name is Nadav and I operate the website
; In the website people can cut-and-paste their C code and it will
"compile" and synthesize it into a Verilog module. You can later
synthesize the core to an FPGA and connect it to a SoC design. The
generated  Verilog is optimized for size, frequency and cycles. The
trade-offs can be decided by the user. I try to parallelize as much as
possible in order to turn  loops into pipelined units. I been working
on the engine for two years now but I only opened the website last
week. I would appreciate any feedback regarding the quality of the
designs, the interfaces for embedded developers, usability, etc.

Nadav Rotem