I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has internal clock where the value is 25 MHz. These clock needs to be divided first in order to can create PWM with 40 kHz frequency and 0.75 duty cycle.Can someone send me a VHDL CODE for a clock divider. Please show by example, I'm new to logic design. Thanks, jebei
vhdl code
Started by ●February 25, 2009
Reply by ●February 25, 20092009-02-25
On Feb 25, 5:49 am, "jebei.jabai" <jebei.ja...@yahoo.com> wrote:> I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has > internal clock where the value is 25 MHz. These clock needs to be divided > first in order to can create PWM with 40 kHz frequency and 0.75 duty > cycle.Can someone send me a VHDL CODE for a clock divider. Please show by > example, I'm new to logic design. > > Thanks, > > jebeiWrong group. Try comp.lang.vhdl Also try <http://www.google.com/search?q=vhdl+tutorial>
Reply by ●February 25, 20092009-02-25
On Wed, 25 Feb 2009 09:28:34 -0800, LittleAlex wrote:> On Feb 25, 5:49 am, "jebei.jabai" <jebei.ja...@yahoo.com> wrote: >> I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has >> internal clock where the value is 25 MHz. These clock needs to be >> divided first in order to can create PWM with 40 kHz frequency and 0.75 >> duty cycle.Can someone send me a VHDL CODE for a clock divider. Please >> show by example, I'm new to logic design. >> >> Thanks, >> >> jebei > > Wrong group. Try comp.lang.vhdl > > Also try <http://www.google.com/search?q=vhdl+tutorial>Or comp.please_do_my_work_for_me -- http://www.wescottdesign.com
