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Cortex M0

Started by steve March 12, 2009
Cortex M3 mini me!

http://www.arm.com/miscPDFs/24481.pdf
On Mar 13, 2:50=A0pm, steve <bungalow_st...@yahoo.com> wrote:
> Cortex M3 mini me! > > http://www.arm.com/miscPDFs/24481.pdf
A wry smile is needed here, after all the hyped-claims about how M3 was going to kick the 8 bit controllers butt.... oops... Yes, NXP claim to have some silicon real soon now... http://www.standardics.nxp.com/products/mcus/cortex-m0/ and they also plan a 3-branch Cortex family. LPC1100 / LPC1300 / LPC1700 http://www.standardics.nxp.com/products/lpc1000/ -jg
On Mar 13, 12:20=A0am, -jg <Jim.Granvi...@gmail.com> wrote:
> On Mar 13, 2:50=A0pm, steve <bungalow_st...@yahoo.com> wrote: > > > Cortex M3 mini me! > > >http://www.arm.com/miscPDFs/24481.pdf > > A wry smile is needed here, after all the hyped-claims about how M3 > was > going to kick the 8 bit controllers butt.... oops... > > Yes, NXP claim to have some silicon real soon now...http://www.standardic=
s.nxp.com/products/mcus/cortex-m0/
> > and they also plan a 3-branch Cortex family. > LPC1100 / LPC1300 / LPC1700http://www.standardics.nxp.com/products/lpc100=
0/
> -jg
I always thought the M3 was a little too much compare with the 8 bitters, with hardware divide and all, still the M0 has 60 instructions, probably 20 is all you need.
On Mar 13, 10:17=A0am, "bungalow_st...@yahoo.com"
<bungalow_st...@yahoo.com> wrote:
> On Mar 13, 12:20=A0am, -jg <Jim.Granvi...@gmail.com> wrote: > > > On Mar 13, 2:50=A0pm, steve <bungalow_st...@yahoo.com> wrote: > > > > Cortex M3 mini me! > > > >http://www.arm.com/miscPDFs/24481.pdf > > > A wry smile is needed here, after all the hyped-claims about how M3 > > was > > going to kick the 8 bit controllers butt.... oops... > > > Yes, NXP claim to have some silicon real soon now...http://www.standard=
ics.nxp.com/products/mcus/cortex-m0/
> > > and they also plan a 3-branch Cortex family. > > LPC1100 / LPC1300 / LPC1700http://www.standardics.nxp.com/products/lpc1=
000/
> > -jg > > I always thought the M3 was a little too much =A0compare with the 8 > bitters, with hardware divide and all, still the M0 has 60 > instructions, probably 20 is all you need.
There we go, NXP seems to have silicon to be showcased during the ESC in San Jose next week! http://www.mcu-related.com/ Another little contribution to the M0 discussion called "Cortex-M0 sense or nonsense" ;-) http://www.mcu-related.com/index.php?limitstart=3D5 An Schwob
On Mar 25, 3:27=A0am, An Schwob in USA <schwo...@aol.com> wrote:
> > There we go, NXP seems to have silicon to be showcased during the ESC > in San Jose next week!http://www.mcu-related.com/
NXP has more brief info here http://www.standardics.nxp.com/literature/leaflets/microcontrollers/pdf/cor= tex-m0.lpc11xx.pdf
> Another little contribution to the M0 discussion called "Cortex-M0 > sense or nonsense" ;-)http://www.mcu-related.com/index.php?limitstart=3D5
Yes, seems to be more marketing than engineering, and rather an admission the M3 is NOT knocking over 8 bit sockets like they hoped! Another admission, was more LPC family parts coming, in 5V spec. It is also unclear what they have removed in M0 opcodes. NXP rep said divide was removed ? ( I got the impression the M0 license fees were much lower... ) The brief above does show they have thrown almost everything overboard on the LPC1100, down to just one uart, one i2c, one spi and no SSC, and a low-end ADC - Targets 48 and 33 pin (32+1?) packages Chasing the bragging rights of the mythical "$1 in volume" perhaps ? -jg
On Mar 24, 12:34 pm, -jg <Jim.Granvi...@gmail.com> wrote:
> On Mar 25, 3:27 am, An Schwob in USA <schwo...@aol.com> wrote: > > > > > There we go, NXP seems to have silicon to be showcased during the ESC > > in San Jose next week!http://www.mcu-related.com/ > > NXP has more brief info herehttp://www.standardics.nxp.com/literature/leaflets/microcontrollers/p... > > > Another little contribution to the M0 discussion called "Cortex-M0 > > sense or nonsense" ;-)http://www.mcu-related.com/index.php?limitstart=5 > > Yes, seems to be more marketing than engineering, and rather > an admission the M3 is NOT knocking over 8 bit sockets like they > hoped! > Another admission, was more LPC family parts coming, > in 5V spec. > > It is also unclear what they have removed in M0 opcodes. > NXP rep said divide was removed ?
the cortex M0 uses the same instruction set as the cortex M1, ARMv6-M, which is a subset of the Thumb-2 (ARMv7) no divide, mac etc see http://electronicdesign.com/files/29/20719/fig_01.gif