PCI FIFO Design

Hello,

I needed to get ideas on how to simulate a FIFO interface on the PCI
interface.  I have a SBC w/ vxWorks and a Communication board in a cPCI
chassis.  The SBC runs an application that feeds data through the PCI
interface to a FIFO on the Comm board.  The Comm board has a number of
control and status registers and receives data through a single 32-bit
memory mapped address (that is the interface to the FIFO on the board).  I
am not allowed to make any modifications to the application running on the
SBC.

For the Comm simulator, I was thinking of using another SBC and
“somehow” configure some of its memory to be setup to respond to the
address range for the Comm board.  Maybe using shared memory.  I could
write a program for this SBC to read the memory mapped registers and react
to what is being written.  I would then “somehow” get an interrupt
whenever any of this memory mapped registers where written to.  It would be
important to respond quickly, especially for the one register interface to
the FIFO. The concern is whether the ISR that copies the data to a buffer
be fast enough to simulate the FIFO interface?

Has anybody done this already?  Can somebody shed light on the
“somehow’s” that I have?  Any other ideas on how to do this
simulation?

Javier

On Mar 31, 12:46=A0pm, "lionhearted" <panora...@hotmail.com> wrote:

> I needed to get ideas on how to simulate a FIFO interface on the PCI
> interface. =A0I have a SBC w/ vxWorks and a Communication board in a cPCI

Buy a single-port PCI serial card with a DIP 16550, remove the 16550
and emulate it with external software and hardware? <http://
tinyurl.com/cwt948>

Use a logic analyzer directly on the PCI bus?

On Tue, 31 Mar 2009 11:46:29 -0500, lionhearted wrote:

> Hello,
> 
> I needed to get ideas on how to simulate a FIFO interface on the PCI
> interface.  I have a SBC w/ vxWorks and a Communication board in a cPCI
> chassis.  The SBC runs an application that feeds data through the PCI
> interface to a FIFO on the Comm board.  The Comm board has a number of
> control and status registers and receives data through a single 32-bit
> memory mapped address (that is the interface to the FIFO on the board). 
> I am not allowed to make any modifications to the application running on
> the SBC.
> 
> For the Comm simulator, I was thinking of using another SBC and
> “somehow” configure some of its memory to be setup to respond to the
> address range for the Comm board.  Maybe using shared memory.  I could
> write a program for this SBC to read the memory mapped registers and
> react to what is being written.  I would then “somehow” get an interrupt
> whenever any of this memory mapped registers where written to.  It would
> be important to respond quickly, especially for the one register
> interface to the FIFO. The concern is whether the ISR that copies the
> data to a buffer be fast enough to simulate the FIFO interface?
> 
> Has anybody done this already?  Can somebody shed light on the
> “somehow’s” that I have?  Any other ideas on how to do this simulation?
> 
> Javier

I doubt that approach would work.  First, dual port memory is special 
stuff, so you'd have to find a SBC that could implement it right off the 
bat.  Second, you'd have to implement the FIFO in software, which would 
severely limit the speed your SBC could respond to input (or to output 
requests).

I suspect that the minimum level of complexity that you'd need for 
success would be an FPGA on a PCI board, and emulate the comm board's 
registers in the FPGA.  This is a doable solution, and I'd be astonished 
if you couldn't buy such a board ready for FPGA firmware off the shelf 
ready for programming.

-- 
http://www.wescottdesign.com

>On Tue, 31 Mar 2009 11:46:29 -0500, lionhearted wrote:
>
>> Hello,
>> 
>> I needed to get ideas on how to simulate a FIFO interface on the PCI
>> interface.  I have a SBC w/ vxWorks and a Communication board in a
cPCI
>> chassis.  The SBC runs an application that feeds data through the PCI
>> interface to a FIFO on the Comm board.  The Comm board has a number of
>> control and status registers and receives data through a single 32-bit
>> memory mapped address (that is the interface to the FIFO on the board).

>> I am not allowed to make any modifications to the application running
on
>> the SBC.
>> 
>> For the Comm simulator, I was thinking of using another SBC and
>> “somehow” configure some of its memory to be setup to respond to
the
>> address range for the Comm board.  Maybe using shared memory.  I could
>> write a program for this SBC to read the memory mapped registers and
>> react to what is being written.  I would then “somehow” get an
interrupt
>> whenever any of this memory mapped registers where written to.  It
would
>> be important to respond quickly, especially for the one register
>> interface to the FIFO. The concern is whether the ISR that copies the
>> data to a buffer be fast enough to simulate the FIFO interface?
>> 
>> Has anybody done this already?  Can somebody shed light on the
>> “somehow’s” that I have?  Any other ideas on how to do this
simulation?
>> 
>> Javier
>
>I doubt that approach would work.  First, dual port memory is special 
>stuff, so you'd have to find a SBC that could implement it right off the

>bat.  Second, you'd have to implement the FIFO in software, which would 
>severely limit the speed your SBC could respond to input (or to output 
>requests).
>
>I suspect that the minimum level of complexity that you'd need for 
>success would be an FPGA on a PCI board, and emulate the comm board's 
>registers in the FPGA.  This is a doable solution, and I'd be astonished

>if you couldn't buy such a board ready for FPGA firmware off the shelf 
>ready for programming.
>
>-- 

Do you have suggestions for any boards  or manufacturer?

>http://www.wescottdesign.com
>

On Tue, 31 Mar 2009 18:06:27 -0500, lionhearted wrote:

>>On Tue, 31 Mar 2009 11:46:29 -0500, lionhearted wrote:
>>
>>> Hello,
>>> 
>>> I needed to get ideas on how to simulate a FIFO interface on the PCI
>>> interface.  I have a SBC w/ vxWorks and a Communication board in a
> cPCI
>>> chassis.  The SBC runs an application that feeds data through the PCI
>>> interface to a FIFO on the Comm board.  The Comm board has a number of
>>> control and status registers and receives data through a single 32-bit
>>> memory mapped address (that is the interface to the FIFO on the
>>> board).
> 
>>> I am not allowed to make any modifications to the application running
> on
>>> the SBC.
>>> 
>>> For the Comm simulator, I was thinking of using another SBC and
>>> “somehow” configure some of its memory to be setup to respond to
> the
>>> address range for the Comm board.  Maybe using shared memory.  I could
>>> write a program for this SBC to read the memory mapped registers and
>>> react to what is being written.  I would then “somehow” get an
> interrupt
>>> whenever any of this memory mapped registers where written to.  It
> would
>>> be important to respond quickly, especially for the one register
>>> interface to the FIFO. The concern is whether the ISR that copies the
>>> data to a buffer be fast enough to simulate the FIFO interface?
>>> 
>>> Has anybody done this already?  Can somebody shed light on the
>>> “somehow’s” that I have?  Any other ideas on how to do this
> simulation?
>>> 
>>> Javier
>>
>>I doubt that approach would work.  First, dual port memory is special
>>stuff, so you'd have to find a SBC that could implement it right off the
> 
>>bat.  Second, you'd have to implement the FIFO in software, which would
>>severely limit the speed your SBC could respond to input (or to output
>>requests).
>>
>>I suspect that the minimum level of complexity that you'd need for
>>success would be an FPGA on a PCI board, and emulate the comm board's
>>registers in the FPGA.  This is a doable solution, and I'd be astonished
> 
>>if you couldn't buy such a board ready for FPGA firmware off the shelf
>>ready for programming.
>>
>>--
> 
> Do you have suggestions for any boards  or manufacturer?

No, it's been ages since I needed to be involved in that, and at the time 
we knew we were going to build something on a custom board, so we just 
used Xilinx's latest PCI eval board.

-- 
http://www.wescottdesign.com