2D array of std_logic_vector in VHDL

Hello all.

I am new to VHDL and I was looking for help crating a 2D array of
std_logic_vectors and initilizing it.


i think i got the first part correct, as there were no errors compiling
and syntesizing in ISE.  

my sytax is
type ARR is array (1 downto 0, 1 downto 0) of std_logic_vector(3 downto
0);
signal my_array : ARR;

now i wanted to initilize the data
i used
  my_array(0,0) <= "0000";
    my_array(0,1) <= "0000";
      my_array(1,0) <= "0000";
        my_array(1,1) <= "0000";

which seems to work, its just that i was looking to see if there were any
other ways to initilze the data maybe with some other notation or comma
separated list, or brackets or somthing.

anyone have any suggestions? Im not sure how efficient this array scheme
is vs an emulated 2D array, im just looking into syntax for now.

thanks in advance

If you use an array of arrays of SLV, you can say:

my_array <= (others => (others => (others => '0')));

I'm not sure if 'others' works with two dimmensional arrays, but I
always use arrays of arrays because then  you can access my_array(i)
[=array of slv], or my_array(i)(j) [=slv], or my_array(i)(j)(k) [=sl].

Andy