TFT LCD controller

On Aug 7, 10:41=A0pm, news.tin.it <djo...@despammed.com> wrote:
> I need some idea to realize a structure like this:
> =A0 =A0 MCU <-> LCD CONTROLLER <-> TFT LCD
>
> I'm using a 32 bit MCU (ARM7 or Cortex-M3), supposed to drive external
> FLASH and SRAM.
> The TFT LCD has to be a QVGA-sized panel with no internal dedicated
> controller, has the company does not want to be be tied to a specific
> display model.
> We have this model to try with:http://www.data-modul.com/de/products/tft_=
displays/single_tft_small/T...
>

Without a controller, you need to bring out 500+ pins to the MCU.
Perhaps you can try a programmable controller with your own interface
spec?

On Aug 7, 2:54=A0pm, news.tin.it <djo...@despammed.com> wrote:

> > Have you considered an FPGA solution?
>
> Yes, but we're still looking at it.
> Any idea?

Well, what are you asking? No I don't have a ready-rolled design in my
back pocket, though likely there is something at opencores that will
serve.

The reason I suggest it is because a simple LCD driver is not a
complex project, and if you do it "soft" then you'll be insulated as
far as possible against parts availability issues.

On Aug 10, 8:13=A0pm, larwe <zwsdot...@gmail.com> wrote:
> On Aug 7, 2:54=A0pm, news.tin.it <djo...@despammed.com> wrote:
>
> > > Have you considered an FPGA solution?
>
> > Yes, but we're still looking at it.
> > Any idea?
>
> Well, what are you asking? No I don't have a ready-rolled design in my
> back pocket, though likely there is something at opencores that will
> serve.
>
> The reason I suggest it is because a simple LCD driver is not a
> complex project, and if you do it "soft" then you'll be insulated as
> far as possible against parts availability issues.

Can you get FPGA in COG die?  Otherwise, 500+ wires between PCB and
LCD would be very expensive, in addition to the expensive FPGA.

Dopo dura riflessione, larwe ha scritto :
> On Aug 7, 2:54&#4294967295;pm, news.tin.it <djo...@despammed.com> wrote:
>
>>> Have you considered an FPGA solution?
>> 
>> Yes, but we're still looking at it.
>> Any idea?
>
> Well, what are you asking? No I don't have a ready-rolled design in my
> back pocket, though likely there is something at opencores that will
> serve.
>
> The reason I suggest it is because a simple LCD driver is not a
> complex project, and if you do it "soft" then you'll be insulated as
> far as possible against parts availability issues.

We're evaluating Lattice FPGA, can you give me some links please?

Thanks

linnix wrote:
> On Aug 7, 10:41 pm, news.tin.it <djo...@despammed.com> wrote:
>> I need some idea to realize a structure like this:
>>     MCU <-> LCD CONTROLLER <-> TFT LCD
>>
>> I'm using a 32 bit MCU (ARM7 or Cortex-M3), supposed to drive external
>> FLASH and SRAM.
>> The TFT LCD has to be a QVGA-sized panel with no internal dedicated
>> controller, has the company does not want to be be tied to a specific
>> display model.
>> We have this model to try with:http://www.data-modul.com/de/products/tft_displays/single_tft_small/T...
>>
> 
> Without a controller, you need to bring out 500+ pins to the MCU.
> Perhaps you can try a programmable controller with your own interface
> spec?
You and the OP have different concepts of controller. The panel linked 
above has a 40 pin connector. It's a pretty typical 6 bit/color 
interface. 500+ pins would be a bit of overkill.

Bob

Scriveva Bob marted�, 11/08/2009:
> 
> You and the OP have different concepts of controller. The panel linked above 
> has a 40 pin connector. It's a pretty typical 6 bit/color interface. 500+ 
> pins would be a bit of overkill.
I think so.
I don't need to tie 500+ pins, as that display has a sort of digital 
interface, hiding all that transistors driving stuff.

The problem is that I can't buy an "intelligent display", one with a 
smart digital interface (I've seen some driven by SPI too): I need a 
general purpose display with that kind of timed interface.

Thanks

On Aug 11, 8:25=A0pm, news.tin.it <djo...@despammed.com> wrote:
> Scriveva Bob marted=EC, 11/08/2009:
>
> > You and the OP have different concepts of controller. The panel linked =
above
> > has a 40 pin connector. It's a pretty typical 6 bit/color interface. 50=
0+
> > pins would be a bit of overkill.
>
> I think so.
> I don't need to tie 500+ pins, as that display has a sort of digital
> interface, hiding all that transistors driving stuff.
>
> The problem is that I can't buy an "intelligent display", one with a
> smart digital interface (I've seen some driven by SPI too): I need a
> general purpose display with that kind of timed interface.
>
> Thanks

But you can do a QVGA controller in a CPLD+RAM, you only need 153600
bytes.
A 128 cell or sort of coolrunner + an SRAM will be plenty.
A mostrous FPGA for that would be way beyond overkill, sounds more
like a madness to me.

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/

Sembra che Dimiter Popoff abbia detto :
> But you can do a QVGA controller in a CPLD+RAM, you only need 153600
> bytes.
> A 128 cell or sort of coolrunner + an SRAM will be plenty.
> A mostrous FPGA for that would be way beyond overkill, sounds more
> like a madness to me.
Hi Dimiter,
we have some external consultant that could do FPGA development on 
Lattice FPGA, as we don't want to begin that kind of work internally.
I've thougth even to a Freescale X-Gate solution, but it would be nice 
only if the company used Freescale MCUs: that's not our case.

Thanks

-- 
http://www.grgmeda.it

On Aug 11, 9:35=A0pm, news.tin.it <djo...@despammed.com> wrote:
> Sembra che Dimiter Popoff abbia detto :> But you can do a QVGA controller=
 in a CPLD+RAM, you only need 153600
> > bytes.
> > A 128 cell or sort of coolrunner + an SRAM will be plenty.
> > A mostrous FPGA for that would be way beyond overkill, sounds more
> > like a madness to me.
>
> Hi Dimiter,
> we have some external consultant that could do FPGA development on
> Lattice FPGA, as we don't want to begin that kind of work internally.
> I've thougth even to a Freescale X-Gate solution, but it would be nice
> only if the company used Freescale MCUs: that's not our case.
>
> Thanks
>
> --http://www.grgmeda.it

What I am saying is that an FPGA is insanely huge for a QVGA display.
The coolrunner is a Xilinx (originally Philips) CPLD and a QVGA
controller should fit comfortably inside. It will take <30 pins for
the
memory interface, apr. 22 for the TFT module interface, and say 16
for an 8 bit processor interface, address decoder included. With
some sweat it might even fit in a 64 cell coolrunner, not that it
is a good idea (I think they discontinued them or are about to do
so).

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/

Dimiter Popoff wrote:

> While Epson show numerous QVGA capable controllers, STM have none
> (just
> VGA -> LCD convertors).
> Siliconmotion are the only ones to my knowledge to make somewhat
> larger
> controllers since the b690x0 by Chips (intel, asiliant) were
> slaughtered.
> http://www.siliconmotion.com/ .

The SM502 is really nice, once you've fixed some bugs in the sample code
they provide, e.g. in the line drawing function. Currently I'm using this
chip in a project. You can get it with integrated RAM and it has fast 2D
graphics acceleration functions. But of course it is BGA, so the OP could
not use it. I think the "no BGA" requirement is a big problem, because most
modern chips with fast LCD controllers are BGA.

Regarding CPLD for a LCD controller: Maybe it is possible to fit something
which scans a framebuffer in 64 cells of a Coolrunner, but graphics update
would be really slow, because I think 2D graphics acceleration are
impossible with 64 cells. But this depends on the application of the OP. A
simple status monitor, where it doesn't matter if the update of the whole
graphics contents needs some 100 ms, should be possible.

Someone in de.sci.electronics has developed a nice new DIL board with a
Xilinx FPGA. I'll design a simple display controller with 2D accleration
function, with SPI interface for small microcontrollers, when I got the
free sample. This is the idea of my design:

http://groups.google.de/group/de.sci.electronics/msg/9ad8c37a29436d54

(the automatic Google translation to English of my posting has not too many
flaws: http://tinyurl.com/r4flsu )

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de