Cypress cover BOTH bases, in a move that has to get everyone's
- Single clock 8051 16/32/64KF, up to 8KR, with up to 67MHz operation,
and 120 part numbers
Wide 1.7-5.5V operation.. LCD drive, 0.5V boost regulator...
0.1% voltage reference (14 ppm/=B0C)
optional 24bx24b MAC
- Cortex parts are 32K-256KF, and up to 64KRam, and 5.5V IO's well...
(but no 32 bit timers?)
Choice of 12b ADC or 20b ADC, CAN, USB...
Tables show 25/38.62 io's on both families - pin compatible
A more complex PLD: UDB is used - text shows 16 cells, but order codes
say 20/24 cells
and each cell has 2 x 12C4 'SPLDs' - that's more complex than earlier
but they also DO expect this to do many of the peripherals - all the
- UDB data mentions datapath Alu/Fifo, which seems to be 8 bits wide,
not clear how that meshes with a 32 bit Cortex?
That's a lot of PLD/Datapath development/debug, that Cypress seems to
bundle into PSoC Creator.
Some corner case examples are needed to get an idea of just what WILL
fit into this
UDB resource. It is more powerful than the wsi/ST PSD families
The C51 core devices look more 'real' than the Cortex ones, on a