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Philosophical placement of counter in vhdl

Started by apalopohapa October 21, 2009
Hello.  I normally have the control description (normally a fsm) 
separate from the datapath.  Supposing I need a counter to time the 
duration of some of the control outputs, for example, enable a shift
register 
for 1000 cycles before doing anything else, would you instantiate the
counter inside or outside of the fsm architecture? 



	   
					
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