Hi everyone, I'm just about to start an implementation of a USB 3.0 interface in VHDL for data transfer from FPGA to a PC and vice versa. The core should acts as a USB device for the PC. The core is intended for an FPGA projects where an "easy" interface to a PC is needed. Higher data rates as defined by the 3.0 standard should be possible with the implementation. Questions are: Does anyone have experience in implementing a USB interface? What are the external chipsets and components respectively required? What about standard compliance? Which standard? Which version? What is the defference between USB Server + USB Client in this respect and which one should I implement to get the desired functionality? Thank You Friends For All Your Kind Support!
USB 3.0 implementation on FPGA
Started by ●March 25, 2010
Reply by ●March 25, 20102010-03-25
"Maurice Branson" <traubenuss@arcor.de> wrote in message news:4bab9732$0$6875$9b4e6d93@newsspool2.arcor-online.net...> Hi everyone, > > > I'm just about to start an implementation of a USB 3.0 interface in VHDL > for data transfer from FPGA to a PC and vice versa. The core should acts > as a USB device for the PC. The core is intended for an FPGA projects > where an "easy" interface to a PC is needed. Higher data rates as defined > by the 3.0 standard should be possible with the implementation. > > > > Questions are: > > Does anyone have experience in implementing a USB interface? > > What are the external chipsets and components respectively required? > > What about standard compliance? Which standard? Which version? > > What is the defference between USB Server + USB Client in this respect and > which one should I implement to get the desired functionality? > > > > Thank You Friends For All Your Kind Support! > > >You will find a lot of information on www.usb.org While I don't mean to be unhelpful the questions you are asking make me feel that you are unlikely to get far with this. USB3 is not easy. If you don't absolutely have to have the USB3 super speed then USB2 high speed (480 Mbit/s) is a lot easier - the 'least brain' approach is to use an FTDI chip for the interface. www.ftdichip.com Michael Kellett
Reply by ●March 25, 20102010-03-25
Thanks, Michael! I will have a look at the URL you postet. Anyway I want this project to be one from which I learn a lot. So I am not interested in the 'least brain' approach but to do as much as I can in VHDL and just use a chipset for the physical link.
Reply by ●March 26, 20102010-03-26
On Mar 25, 6:41=A0pm, "Maurice Branson" <trauben...@arcor.de> wrote:> Thanks, Michael! > > I will have a look at the URL you postet. Anyway I want this project to b=e> one from which I learn a lot. So I am not interested in the 'least brain' > approach but to do as much as I can in VHDL and just use a chipset for th=e> physical link.First of all you should go to USB implementers forum USB-IF and download the specifications of USB 3.0 (which will include host/device/ hub specification). Than you have to read and read and read again to fully understand the USB 3.0. I hope you know that this won't be a project that you will finish in a month or two. I would estimate that one person would spend about 8 hours a day on USB 3.0 one could probably finish it in 12 months (but that might be too optimistic, since the development of USB 3.0 device takes about 6-9 months for a team of HDL developers :)) If you want to learn something first try using ready USB 2.0 chip and implement full hardware control of the chip without any CPU.
Reply by ●March 26, 20102010-03-26
wojtek <wojtekpowiertowski@gmail.com> wrote>On Mar 25, 6:41�pm, "Maurice Branson" <trauben...@arcor.de> wrote: >> Thanks, Michael! >> >> I will have a look at the URL you postet. Anyway I want this project to be >> one from which I learn a lot. So I am not interested in the 'least brain' >> approach but to do as much as I can in VHDL and just use a chipset for the >> physical link. > >First of all you should go to USB implementers forum USB-IF and >download the specifications of USB 3.0 (which will include host/device/ >hub specification). Than you have to read and read and read again to >fully understand the USB 3.0. I hope you know that this won't be a >project that you will finish in a month or two. I would estimate that >one person would spend about 8 hours a day on USB 3.0 one could >probably finish it in 12 months (but that might be too optimistic, >since the development of USB 3.0 device takes about 6-9 months for a >team of HDL developers :)) If you want to learn something first try >using ready USB 2.0 chip and implement full hardware control of the >chip without any CPU.I would buy a USB chip. The protocol is a total mess and always has been. I don't know if FTDI do a '3 chip but their standard ones work really well.
Reply by ●March 26, 20102010-03-26
Maurice> I will have a look at the URL you postet. Anyway I want this project to be > one from which I learn a lot. So I am not interested in the 'least brain' > approach but to do as much as I can in VHDL and just use a chipset for the > physical link.USB 3.0 requires that a device (peripheral) support the new "Super Speed" *and* at least one other speed (low, full or high). So, in many ways, you would be better doing a USB2.0 device and sticking on a suitable USB PHY for the physical interface. There aren't many USB 3.0 hosts around yet against which you could test your device either: lots of USB 2.0 stuff though! Andrew
Reply by ●March 26, 20102010-03-26
"Andrew Jackson" <alj@nospam.com> wrote news:X_adnaUfiO556jHWnZ2dnUVZ8l2dnZ2d@eclipse.net.uk...> ways, you would be better doing a USB2.0 device and sticking on a suitable > USB PHY for the physical interface. There aren't many USB 3.0 hosts > around yet against which you could test your device either: lotsThanks, Andrew! Sounds resonable to me. So if I start with 2.0 is there a compatibility that I may "expand" my design to a 3.0 core or is it totally different? I learned from what I've read here and in the www that I need at least a separate PHY because that is something that I cannot to in the FPGA fabric. Are there any USB 3.0 PHYs already available? Found nothing. :-( KR Maurica
Reply by ●March 26, 20102010-03-26
On Mar 26, 11:18=A0am, "Maurice Branson" <trauben...@arcor.de> wrote:> "Andrew Jackson" <a...@nospam.com> wrotenews:X_adnaUfiO556jHWnZ2dnUVZ8l2d=nZ2d@eclipse.net.uk...> > > ways, you would be better doing a USB2.0 device and sticking on a suita=ble> > USB PHY for the physical interface. =A0There aren't many USB 3.0 hosts > > around yet against which you could test your device either: lots > > Thanks, Andrew! > > Sounds resonable to me. So if I start with 2.0 is there a compatibility t=hat> I may "expand" my design to a 3.0 core or is it totally different? I lear=ned> from what I've read here and in the www that I need at least a separate P=HY> because that is something that I cannot to in the FPGA fabric. Are there =any> USB 3.0 PHYs already available? Found nothing. :-( > > KR Maurica3.0 core is basically separate from 2.0 on almost every layer, if you have a usb 3.0 device it tries to connect using super speed and if that is not available on the other side, the 3.0 core shuts down and 2.0/1.1 core starts its operation. The PHY is not publicly available, because there is no market for it, right now only big companies working on usb 3.0 appliances (like WD, Samsung, Intel, ...) have it available.
Reply by ●March 26, 20102010-03-26
On Mar 26, 1:30=A0pm, wojtek <wojtekpowiertow...@gmail.com> wrote:> On Mar 26, 11:18=A0am, "Maurice Branson" <trauben...@arcor.de> wrote: > > > "Andrew Jackson" <a...@nospam.com> wrotenews:X_adnaUfiO556jHWnZ2dnUVZ8l=2dnZ2d@eclipse.net.uk...> > > > ways, you would be better doing a USB2.0 device and sticking on a sui=table> > > USB PHY for the physical interface. =A0There aren't many USB 3.0 host=s> > > around yet against which you could test your device either: lots > > > Thanks, Andrew! > > > Sounds resonable to me. So if I start with 2.0 is there a compatibility=that> > I may "expand" my design to a 3.0 core or is it totally different? I le=arned> > from what I've read here and in the www that I need at least a separate=PHY> > because that is something that I cannot to in the FPGA fabric. Are ther=e any> > USB 3.0 PHYs already available? Found nothing. :-( > > > KR Maurica > > 3.0 core is basically separate from 2.0 on almost every layer, if you > have a usb 3.0 device it tries to connect using super speed and if > that is not available on the other side, the 3.0 core shuts down and > 2.0/1.1 core starts its operation. The PHY is not publicly available, > because there is no market for it, right now only big companies > working on usb 3.0 appliances (like WD, Samsung, Intel, ...) have it > available.well, USB 3.0 is the first one that needs NO PHY as the MGT's in some newer FPGA's are USB 3.0 capable directly just wire MGT to usb 3.0 superspeed pins, and that about it Antti
Reply by ●March 26, 20102010-03-26
On Mar 26, 1:58=A0pm, Antti <antti.luk...@googlemail.com> wrote:> well, USB 3.0 is the first one that needs NO PHY > > as the MGT's in some newer FPGA's are USB 3.0 capable directly > just wire MGT to usb 3.0 superspeed pins, and that about it > > AnttiThat is the first time i hear abou MGT being compatible with USB 3.0 PHY, but I haven't doing anything in USB 3.0 topic for almost a year. I must say I find it hard to believe thought, because USB 3.0 besides translating digital signal to differential analog signal also transmits USB 3.0 specific LFPS (low frequency pulse signaling) and from what I learned the USB 3.0 PHY was supposed to take care of that (just like latest PCI express PHY, which has similar LFPS technology). I believe the MGT doesn't support that. But as I've said I hadn't even researched it for some time, so I might be wrong.
