Cypress FX2 buffering

Hello,
I have a question concerning the double, tripple, quad buffering process
in
the FX2.

Are the folowing statements correct: 
Quad buffering, IN Endpoint: The external master can fill one buffer while
the PC is emptying the other three buffers.

Full flag: ALL buffers are filled
Empty flag: ALL buffers are empty.


Quad buffering, IN Endpoint: Is it right, that for example when I write
one
buffer full of data, the fifo logic automaticly switches the buffer and
the
folowing data is written into the new buffer? And in the time, while the
new buffer is filled, the PC (host) can empty the old buffer?

Best regards
Jan
	   
					
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The last time I used this chip was 1 year ago, so if I answer from memory,  
I could be wrong ;)

So if you'd like, I can send you C source code which runs on the FX2 for  
usb bulk data transfers (tested at more than 40 MB/s, transferring to a  
FPGA).

>
>The last time I used this chip was 1 year ago, so if I answer from memory,
 
>I could be wrong ;)
>
>So if you'd like, I can send you C source code which runs on the FX2 for 

>usb bulk data transfers (tested at more than 40 MB/s, transferring to a  
>FPGA).
>

Thank you, but I have source codes myself. I realy like to know how the
buffering works. In example the quad buffering	   
					
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It is some time since I used an FX2 but from looking at various notes:

> I have a question concerning the double, tripple, quad buffering
> process in the FX2.
>
> Are the folowing statements correct:
>
> Quad buffering, IN Endpoint: The external master can fill one buffer
> while the PC is emptying the other three buffers.

Yes, provided that you are not trying to fill the FIFOs with short packets.

> Full flag: ALL buffers are filled Empty flag: ALL buffers are empty.

Yes.

> Quad buffering, IN Endpoint: Is it right, that for example when I
> write one buffer full of data, the fifo logic automaticly switches
> the buffer and the folowing data is written into the new buffer? And
> in the time, while the new buffer is filled, the PC (host) can empty
> the old buffer?

Yes, if you set the AUTOIN mode.  This also depends on how you fill the 
slave FIFOs and how PKTEND is asserted (for short packets).

Have you looked at the EZ-USB technical reference manual: it should 
answer most of your questions.


	Andrew

> It is some time since I used an FX2 but from looking at various notes:
>
>> I have a question concerning the double, tripple, quad buffering
>> process in the FX2.
>>
>
>> Full flag: ALL buffers are filled Empty flag: ALL buffers are empty.
>
> Yes.

P.S. If you want to have a flag specifying some intermediate level use 
the "programmable flag" option.

	Andrew

>It is some time since I used an FX2 but from looking at various notes:
>
>> I have a question concerning the double, tripple, quad buffering
>> process in the FX2.
>>
>> Are the folowing statements correct:
>>
>> Quad buffering, IN Endpoint: The external master can fill one buffer
>> while the PC is emptying the other three buffers.
>
>Yes, provided that you are not trying to fill the FIFOs with short
packets.




So can it be that the full flag will never be asserted, because (when
filling the FIFO) the whole four buffers are never full, because the FX2
sends the buffer immediately to the PC-host?



>
>> Full flag: ALL buffers are filled Empty flag: ALL buffers are empty.
>
>Yes.
>
>> Quad buffering, IN Endpoint: Is it right, that for example when I
>> write one buffer full of data, the fifo logic automaticly switches
>> the buffer and the folowing data is written into the new buffer? And
>> in the time, while the new buffer is filled, the PC (host) can empty
>> the old buffer?
>
>Yes, if you set the AUTOIN mode.  This also depends on how you fill the 
>slave FIFOs and how PKTEND is asserted (for short packets).

Ok, when PKTEND is asserted the data will be sent to the host.

>
>Have you looked at the EZ-USB technical reference manual: it should 
>answer most of your questions.

Yes, I look in the TRM. But in my opinion, the relationships between
buffering and sending the frame are not clearly decribed there.
>
>
>	Andrew
>
>

	   
					
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> Yes, I look in the TRM. But in my opinion, the relationships between
> buffering and sending the frame are not clearly decribed there.

IIRC (at least in one mode of operation) the frame is sent ONLY when
you you either fill the buffer completely, or when you assert PKTEND
to indicate that you want a short buffer to be sent.

>> Yes, I look in the TRM. But in my opinion, the relationships between
>> buffering and sending the frame are not clearly decribed there.
>
>IIRC (at least in one mode of operation) the frame is sent ONLY when
>you you either fill the buffer completely, or when you assert PKTEND
>to indicate that you want a short buffer to be sent.
>
the buffers completely ... or one buffer completely?

sorry but.. I don't find the information in the trm.	   
					
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>>> Yes, I look in the TRM. But in my opinion, the relationships between
>>> buffering and sending the frame are not clearly decribed there.
>>
>> IIRC (at least in one mode of operation) the frame is sent ONLY when
>> you you either fill the buffer completely, or when you assert PKTEND
>> to indicate that you want a short buffer to be sent.
>>
> the buffers completely ... or one buffer completely?
>

As Marc says, you can indicate that a FIFO buffer is filled either 
implicitly by putting at least <endpoint_size> bytes into it or by 
explicitly asserting the PKTEND signal (or its software equivalent).

The FX2 effectively translates from a continuous byte-stream to the 
packet-stream required by USB.  So if your hardware, or firmware, just 
fills the FIFO buffers then, as each endpoint sized buffer is filled it 
can be sent to the USB host.  If your hardware can fill faster than the 
USB host can extract the data then the FIFO full flag will be asserted.

You should be able to test this behaviour using CyConsole.

	Andrew

Ok thank you.

But I have a further question.

I configure the FIFO as quad-buffered. All buffers are full of data. How
long takes is till the FIFO is rewritable. Does it last several CLK
cycles?	   
					
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