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xmega slave spi problem

Started by theAdib November 5, 2010
Hi all,

i'am hunting this problem since a couple of days ...
All I need is are 2 synchronous serial data-streams for my selfmade
modulator. the clock phase must be in synch.

My idea was to use a master spi to generate the master stream and a
spi slave module as second generator that is clocked by the clock out
put from the first master.

For the first I use USART in master spi mode. for the second I tried
the SPI module in slave mode and usart module in synchrounus slave
mode.
the first one fails because I can not put a second byte to the data
register. It is not shifted out until the /SS is deactivated and
activated again. Also because there is no double buffering there is
virtually no time to update the data register.
The second somehow fails. And I don't know why. when I try to send a
0xAA pattern. sometimes there are two same bits following.

My system is XMega A1 running on 15MHz and the bit time is 2.5usec.

Anyone else having problems on this slave implementations?

Thanks,

Adib.
I just let you know that somehow I solved my problems.

I now go for the DMA service as explained in the Application note from
Atmel: AVR1510: Xplain training - XMEGA USART

There is only a little timeslot to update the SPI Slave data register.
In my example there are two DMA:
- DMA0 for USART in SPI master mode, triggered on DRE interrupt event
- DMA1 for SPI in SPI slave mode, triggered on transmission complete
interrupt.

I have to make shure the cpu does not much proccessing, bcs this can
delay the DMA to the slave cpu. So that DATA register might not
updated in time.

However, I did not found the way to work in interrupt mode for this
frequency constellation.

Cheers,

Adib.




On Nov 5, 8:16=A0pm, theAdib <thea...@googlemail.com> wrote:
> Hi all, > > i'am hunting this problem since a couple of days ... > All I need is are 2 synchronous serial data-streams for my selfmade > modulator. the clock phase must be in synch. > > My idea was to use a master spi to generate the master stream and a > spi slave module as second generator that is clocked by the clock out > put from the first master. > > For the first I use USART in master spi mode. for the second I tried > the SPI module in slave mode and usart module in synchrounus slave > mode. > the first one fails because I can not put a second byte to the data > register. It is not shifted out until the /SS is deactivated and > activated again. Also because there is no double buffering there is > virtually no time to update the data register. > The second somehow fails. And I don't know why. when I try to send a > 0xAA pattern. sometimes there are two same bits following. > > My system is XMega A1 running on 15MHz and the bit time is 2.5usec. > > Anyone else having problems on this slave implementations? > > Thanks, > > Adib.