debugging pointers required

Hi,
I am using a spartan 3 xc3s4000 FPGA in my custom design which is
interfaced with national gigabit PHYs DP83865dvh. It is actually an
Ethernet mac and the design is like this:
 PHY A <--> FPGA  <--> PHY B

The problem is that sometimes, not always, i get one or two packet drops
when i put the systems on test. I tested only one unit using chariot for
throughput, no packet drops. But when i test the units in pair, sometimes i
get a few packet drops, sometimes i don't get any packet drops. The test
durations are usually from 1hour to 2hours. The packet drop always occurs
on the generating end i.e. the system generating the stream.

So, to see why the packet was dropping, i used chipscope in FPGA and i saw
that the data that comes in to the FPGA, there's always 1 corrupt byte in
the dropped packet that leads to CRC failure and the system drops it. I
tried to see if the bits getting corrupt were always the same but they were
different each time. So, I started looking at the power requirements and
temperature ranges of my devices and found nothing that could lead to such
a behavior. First I thought maybe it's the FPGA timing problem as the byte
always gets corrupt at the first FF inside FPGA, but had it been a problem,
it would have occurred more frequently, not sometimes.

I also ran a ping test with packet size 65000Bytes and same problem
existed.It doesn't occur in small packets.
Now, i am out of ideas to debug this problem so i need your help in this
regard.

Kindly give me some pointers to look for so that i can solve the problem
asap.


Regards
 	   
					
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