Forums

large microprocessors?

Started by Paul Rubin February 3, 2013
I notice that the ram capacity (ignore program flash for now, but it
tends to basically be proportionate) of microcontrollers seems to grow
fairly continuously (say in 2x jumps) from very small (a dozen or so
bytes in an 8 bitter, lots of MSP430's in the 128 to 1k byte range,
Cortex M0's with 4k, etc.), up to about 32k (Cortex M4).  Above that
there are a few chips with 64k or 128k, that are quite expensive, and
above that not much is available til you get to external DRAM which on
ready-made boards usually starts at 32 meg or even 64 meg (Olimex
Olinuxino) or 512 meg (Raspberry Pi).  So there is a big jump from 32k
to 32 meg.  It would be nice to have a low cost, single chip, 256k or 1
megabyte device but this doesn't seem to exist.

Is there some technical reason for this, or is it just a
market-determined thing?  I know that desktop cpu's often have megabytes
of sram cache, so it's certainly technologically feasible to do
something similar with a smaller cpu.

Thanks.
On Sat, 02 Feb 2013 22:17:29 -0800, Paul Rubin
<no.email@nospam.invalid> wrote:

>I notice that the ram capacity (ignore program flash for now, but it >tends to basically be proportionate) of microcontrollers seems to grow >fairly continuously (say in 2x jumps) from very small (a dozen or so >bytes in an 8 bitter, lots of MSP430's in the 128 to 1k byte range, >Cortex M0's with 4k, etc.), up to about 32k (Cortex M4). Above that >there are a few chips with 64k or 128k, that are quite expensive, and >above that not much is available til you get to external DRAM which on >ready-made boards usually starts at 32 meg or even 64 meg (Olimex >Olinuxino) or 512 meg (Raspberry Pi). So there is a big jump from 32k >to 32 meg. It would be nice to have a low cost, single chip, 256k or 1 >megabyte device but this doesn't seem to exist. > >Is there some technical reason for this, or is it just a >market-determined thing? I know that desktop cpu's often have megabytes >of sram cache, so it's certainly technologically feasible to do >something similar with a smaller cpu.
On-chip ran is usually SRAM, and that's usually at least a factor of six time less dense than DRAM, so large on-chip memories usually require fairly large dies. And it's worse in practice since most microcontrollers are not implemented in the latest processes, and DRAM process are highly optimized for density, both of which multiply the overhead. Things like eDRAM are possible, but require considerable extra processing in the fab, so are largely impossible from a cost perspective for low cost devices. Since external DRAMs are (mostly) commodity items, the price pressure on the manufacturers are severe, leading to excellent price per bit. Smaller external DRAMs are certainly possible, but there's not much of a price break below 32MB or so. I suspect we'll see stacked dies before too long, which would provide the large capacity without the hassle of an external DRAM.
Paul Rubin <no.email@nospam.invalid> wrote:

 >Cortex M0's with 4k, etc.), up to about 32k (Cortex M4).  Above that
 >there are a few chips with 64k or 128k, that are quite expensive, and
 >above that not much is available til you get to external DRAM which on

Nope. Renesas SH7262 1024k. A very nice toy. Very powerful. .-)

 >to 32 meg.  It would be nice to have a low cost, single chip, 256k or 1
 >megabyte device but this doesn't seem to exist.

It is existing. You did not search good enough.

But it is only need for a few application and so it is
expensive. (arround 10Euro for high volume, 20Euro if you buy a few)
 
This is my prototypboard:
http://www.criseis.ruhr.de/bilder/mp3_1.jpg

You see the advantage? The huge internal sram made it possible to use
this kind of controller on a selfmade twoside PCB.  

Play some music:
http://www.criseis.ruhr.de/bilder/mp3_2.jpg

Good enought for playing 320kbit MP3 with libmad.

Olaf
Olaf Kaluza <olaf@criseis.ruhr.de> writes:
> Nope. Renesas SH7262 1024k. A very nice toy. Very powerful. .-)
Thanks. This appears to be an older and rather expensive part with a not-so-common architecture (Hitachi SH2) but it's good to know about.
On 03/02/13 07.17, Paul Rubin wrote:
> I notice that the ram capacity (ignore program flash for now, but it > tends to basically be proportionate) of microcontrollers seems to grow > fairly continuously (say in 2x jumps) from very small (a dozen or so > bytes in an 8 bitter, lots of MSP430's in the 128 to 1k byte range, > Cortex M0's with 4k, etc.), up to about 32k (Cortex M4). Above that > there are a few chips with 64k or 128k, that are quite expensive, and > above that not much is available til you get to external DRAM which on > ready-made boards usually starts at 32 meg or even 64 meg (Olimex > Olinuxino) or 512 meg (Raspberry Pi). So there is a big jump from 32k > to 32 meg. It would be nice to have a low cost, single chip, 256k or 1 > megabyte device but this doesn't seem to exist. > > Is there some technical reason for this, or is it just a > market-determined thing? I know that desktop cpu's often have megabytes > of sram cache, so it's certainly technologically feasible to do > something similar with a smaller cpu. > > Thanks.
Hi Paul The newest (for me) is ARM with PoP memory with higher RAM/flash is needed. But they might be a nightmare minimize solder ball defects. But alternative to let the package sit beside the microprocessor is worse because then more PCB copper layers are needed: http://en.wikipedia.org/wiki/Package_on_package Quote: "... Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras. ..." Example of PoP usage - only possible because ARM are so low-power: http://beagleboard.org/ GTA04 GTA04A5 with 1GiB flash and 1GHz ARM: http://projects.goldelico.com/p/gta04-main/ http://projects.goldelico.com/p/gta04-main/doc/ Manual and schematic for GTA04 revision A3...A5: http://projects.goldelico.com/p/gta04-main/page/Manual/ Glenn
Glenn <glenn2233@gmail.com> writes:
> http://en.wikipedia.org/wiki/Package_on_package
Thanks, I remember seeing that on the original Beagleboard but I was more interested in what was around on single chips.
> GTA04 GTA04A5 with 1GiB flash and 1GHz ARM:
Wow, cool, though too expensive for me to think about ;-). I like that the Open Moko concept is still alive but I think it's better to have a data-only device and a separate phone.
On Sun, 03 Feb 2013 00:39:15 -0600, Robert Wessel
<robertwessel2@yahoo.com> wrote:

>On-chip ran is usually SRAM, and that's usually at least a factor of >six time less dense than DRAM, so large on-chip memories usually >require fairly large dies. And it's worse in practice since most >microcontrollers are not implemented in the latest processes, and DRAM >process are highly optimized for density, both of which multiply the >overhead.
Putting DRAM on chip would have some interesting architectural features. Assuming 2 MiB DRAM = 16 Mib organized as 4096x4096 bits. The 12 high order bit will activate a row and all the 4096 bits in the column go through the column amplifiers back to the original cells. As a side product, all the 4096 column bits (512 bytes) could be latched in parallel, while a typical external DRAM uses a data selector to select a few bits or few bytes before latched out to external pins. With all column bits latched on-chip, this would act also as a cache for "free", as long as the access is within the same 512 byte column. To significantly reduce miss rates, use separate 512 byte latches for data and instructions.
Paul Rubin <no.email@nospam.invalid> wrote:

 >Thanks.  This appears to be an older and rather expensive part with a
 >not-so-common architecture (Hitachi SH2) but it's good to know about.

It is an SH2A. This has some advantage over the old SH2. For example
16 register bank for a fast IRQ. 

Olaf
  
On Sun, 03 Feb 2013 10:05:43 +0200, upsidedown@downunder.com wrote:

>On Sun, 03 Feb 2013 00:39:15 -0600, Robert Wessel ><robertwessel2@yahoo.com> wrote: > >>On-chip ran is usually SRAM, and that's usually at least a factor of >>six time less dense than DRAM, so large on-chip memories usually >>require fairly large dies. And it's worse in practice since most >>microcontrollers are not implemented in the latest processes, and DRAM >>process are highly optimized for density, both of which multiply the >>overhead. > >Putting DRAM on chip would have some interesting architectural >features. Assuming 2 MiB DRAM = 16 Mib organized as 4096x4096 bits. >The 12 high order bit will activate a row and all the 4096 bits in the >column go through the column amplifiers back to the original cells. As >a side product, all the 4096 column bits (512 bytes) could be latched >in parallel, while a typical external DRAM uses a data selector to >select a few bits or few bytes before latched out to external pins. > >With all column bits latched on-chip, this would act also as a cache >for "free", as long as the access is within the same 512 byte column. >To significantly reduce miss rates, use separate 512 byte latches for >data and instructions.
You're basically describing fast-page-mode DRAM. The problem of integrating DRAM onto a logic process remains, however. OTOH, you could do the exactly same thing on an SRAM array if you wanted.
On Sat, 02 Feb 2013 22:17:29 -0800, Paul Rubin
<no.email@nospam.invalid> wrote:

>So there is a big jump from 32k >to 32 meg. It would be nice to have a low cost, single chip, 256k or 1 >megabyte device but this doesn't seem to exist.
STM32F4xx have 192kb or 256kb RAM and 1Mb or more of Flash. These are excellent Cortex-M4 devices. Stephen -- Stephen Pelc, stephenXXX@mpeforth.com MicroProcessor Engineering Ltd - More Real, Less Time 133 Hill Lane, Southampton SO15 5AF, England tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691 web: http://www.mpeforth.com - free VFX Forth downloads