Market size of new, non-legacy, 5V ICs ?

rickman <gnuarm@gmail.com> wrote:
> I have not found an FPGA tolerant of 5 volt signals.  I had to add 
> two 24 pin Quickswitch parts as buffers to a design I did a while 
> back.  FPGA folks just don't feel there is market enough to take the 
> hit in whatever they would need to take the hit in for 5 volt 
> tolerant I/Os.

SiliconBlue's iCE65 _was_ 5V tolerant, so of course Lattice immediately 
killed it off when they bought the company.

-a

On 3/23/2013 7:30 PM, Anders.Montonen@kapsi.spam.stop.fi.invalid wrote:
> rickman<gnuarm@gmail.com>  wrote:
>> I have not found an FPGA tolerant of 5 volt signals.  I had to add
>> two 24 pin Quickswitch parts as buffers to a design I did a while
>> back.  FPGA folks just don't feel there is market enough to take the
>> hit in whatever they would need to take the hit in for 5 volt
>> tolerant I/Os.
>
> SiliconBlue's iCE65 _was_ 5V tolerant, so of course Lattice immediately
> killed it off when they bought the company.

Yes, I sorely miss the iCE65, "Johnny we hardly knew Ye".  It also had a 
much lower static current than the iCE40.  But even in the low power/low 
price market there is only so much need for low static currents and 5 
volt tolerance.

I recall getting price quotes of under $3 for 100 pin devices.  At that 
price it would have been good enough to replace nearly any MSI logic on 
a board.  You don't even have to program them as they will deliver them 
pre-programmed.

-- 

Rick

rickman <gnuarm@gmail.com> writes:

> I have not found an FPGA tolerant of 5 volt signals.

Yeah, I guess those are long gone. Altera still has internal clamp
diodes in larger MaxII CPLDs which makes them 5V tolerant. But only as
long as you make sure the CPLD is powered and configured before any pin
can go to 5V...

On 3/26/2013 5:31 AM, Anssi Saari wrote:
> rickman<gnuarm@gmail.com>  writes:
>
>> I have not found an FPGA tolerant of 5 volt signals.
>
> Yeah, I guess those are long gone. Altera still has internal clamp
> diodes in larger MaxII CPLDs which makes them 5V tolerant. But only as
> long as you make sure the CPLD is powered and configured before any pin
> can go to 5V...

Actually it is the clamp diodes that makes them 5 volt *intolerant*.  If 
you apply greater than Vdd the clamp diodes conduct and the two power 
supplies fight it out with the diode in the middle.  Who do you think 
wins that battle?

I guess you are referring to adding a series resistor to limit the 
current.  That works ok on inputs but on outputs it has to be a resistor 
pullup which has slew rate issues in fast designs.

When I talk about 5 volt tolerance, I mean putting 5 volts directly on 
the FPGA I/O pin.  Without the clamp diode, as long as the gate oxide of 
the input will take 5 volts, the I/O pin will handle the drive.  But the 
FPGA makers keep thinning the gate oxide and don't want to have a 
separate step in the process for a thicker I/O gate oxide layer.  So 
it's "goodbye" to 5 volt tolerance.

Heck, I remember Xilinx was talking about doing away with 3.3 volt 
tolerance.  They seem to think their primary markets were all 
transitioning to 2.5 and 1.8 volt busses for internal (to the board) 
signals.  I guess they want to get the oxide layers down to a single 
atom thick.

-- 

Rick

On 27 Mar., 16:07, rickman <gnu...@gmail.com> wrote:
> On 3/26/2013 5:31 AM, Anssi Saari wrote:
>
> > rickman<gnu...@gmail.com> &#4294967295;writes:
>
> >> I have not found an FPGA tolerant of 5 volt signals.
>
> > Yeah, I guess those are long gone. Altera still has internal clamp
> > diodes in larger MaxII CPLDs which makes them 5V tolerant. But only as
> > long as you make sure the CPLD is powered and configured before any pin
> > can go to 5V...
>
> Actually it is the clamp diodes that makes them 5 volt *intolerant*. &#4294967295;If
> you apply greater than Vdd the clamp diodes conduct and the two power
> supplies fight it out with the diode in the middle. &#4294967295;Who do you think
> wins that battle?
>
> I guess you are referring to adding a series resistor to limit the
> current. &#4294967295;That works ok on inputs but on outputs it has to be a resistor
> pullup which has slew rate issues in fast designs.

I believe xilinx has had two different ways to do 5V "tolerance",

one is the series resistor clamping with the esd diode to the,
usually, 3.3V io supply

the other didn't have an esd diode to the supply but instead a ~5V
clamp to ground
that was more like real 5V tolerance, it was for 5V pci I think

>
> When I talk about 5 volt tolerance, I mean putting 5 volts directly on
> the FPGA I/O pin. &#4294967295;Without the clamp diode, as long as the gate oxide of
> the input will take 5 volts, the I/O pin will handle the drive. &#4294967295;But the
> FPGA makers keep thinning the gate oxide and don't want to have a
> separate step in the process for a thicker I/O gate oxide layer. &#4294967295;So
> it's "goodbye" to 5 volt tolerance.
>
> Heck, I remember Xilinx was talking about doing away with 3.3 volt
> tolerance. &#4294967295;They seem to think their primary markets were all
> transitioning to 2.5 and 1.8 volt busses for internal (to the board)
> signals. &#4294967295;I guess they want to get the oxide layers down to a single
> atom thick.
>

if you want high speed and low price you need to go small, small
means
lower voltage

-Lasse

On Thursday, March 28, 2013 8:34:03 AM UTC+12, lang...@fonz.dk wrote:
> 
> I believe xilinx has had two different ways to do 5V "tolerance",
> one is the series resistor clamping with the esd diode to the,
> usually, 3.3V io supply
 
 That is a kludge, and the part itself cannot properly be called 5V tolerant.

 Even the ones that are ONLY 5V tolerant, when powered, are not properly 5V tolerant.
 
> the other didn't have an esd diode to the supply but instead a ~5V
> clamp to ground
> that was more like real 5V tolerance, it was for 5V pci I think

 This is what the Logic market now does.
After a brief flirtation with 3V only, LVC parts are properly 5V tolerant, and allow any Vcc conditions. 
 They sometimes call this Ioff, and these parts use an avalanch FET structure as the ESD clamp.

> 
> if you want high speed and low price you need to go small, small
> means lower voltage

That is true of the core logic, but almost every part above a moderate size these days, has a Core Vcc, and many have Multiple Oxide choices. 

So the issue is mainly in the IO-Ring, and for FPGA vendors, who tend to be ns-obsessed, 5V is off their radar.

The uC and Logic vendors prove there is no technical or cost barrier, to offering 5V, with low voltage cores.
They also understand it expands their market.

A possible FPGA compromise would be to have one IO bank 5V tolerant, - that would incur the small speed impact in one bank, but users can choose IO and it is rare you need ALL 5V tolerant, or ALL highest speed.

-jg

On 3/27/2013 4:34 PM, langwadt@fonz.dk wrote:
> On 27 Mar., 16:07, rickman<gnu...@gmail.com>  wrote:
>> On 3/26/2013 5:31 AM, Anssi Saari wrote:
>>
>>> rickman<gnu...@gmail.com>    writes:
>>
>>>> I have not found an FPGA tolerant of 5 volt signals.
>>
>>> Yeah, I guess those are long gone. Altera still has internal clamp
>>> diodes in larger MaxII CPLDs which makes them 5V tolerant. But only as
>>> long as you make sure the CPLD is powered and configured before any pin
>>> can go to 5V...
>>
>> Actually it is the clamp diodes that makes them 5 volt *intolerant*.  If
>> you apply greater than Vdd the clamp diodes conduct and the two power
>> supplies fight it out with the diode in the middle.  Who do you think
>> wins that battle?
>>
>> I guess you are referring to adding a series resistor to limit the
>> current.  That works ok on inputs but on outputs it has to be a resistor
>> pullup which has slew rate issues in fast designs.
>
> I believe xilinx has had two different ways to do 5V "tolerance",
>
> one is the series resistor clamping with the esd diode to the,
> usually, 3.3V io supply

Unfortunately this doesn't work in the general case.  The series 
resistor slows the rise time of the input significantly.  This also does 
not address the issue with outputs at all.


> the other didn't have an esd diode to the supply but instead a ~5V
> clamp to ground
> that was more like real 5V tolerance, it was for 5V pci I think

A 5 volt clamp or a 3 volt clamp?  If they used a 5 volt clamp that 
implies that 5 volts on the I/O pin is acceptable and that indeed is 
true 5 volt tolerance.


>> When I talk about 5 volt tolerance, I mean putting 5 volts directly on
>> the FPGA I/O pin.  Without the clamp diode, as long as the gate oxide of
>> the input will take 5 volts, the I/O pin will handle the drive.  But the
>> FPGA makers keep thinning the gate oxide and don't want to have a
>> separate step in the process for a thicker I/O gate oxide layer.  So
>> it's "goodbye" to 5 volt tolerance.
>>
>> Heck, I remember Xilinx was talking about doing away with 3.3 volt
>> tolerance.  They seem to think their primary markets were all
>> transitioning to 2.5 and 1.8 volt busses for internal (to the board)
>> signals.  I guess they want to get the oxide layers down to a single
>> atom thick.
>>
>
> if you want high speed and low price you need to go small, small
> means
> lower voltage

Lower voltage on the supply, but that is not the same as lower I/O 
voltages.  There are any number of MCU makers who are providing chips 
with low core voltages for the newer process devices with 5 volt 
tolerance on the I/Os.  So it can be done, you just need the *will* to 
do it.  I believe Xilinx dropped 5 volt tolerance somewhere around 
120-150 nm while many MCU makers are pumping out devices at the 90 nm 
process node which still have 5 volt tolerance.

Like I said, Xilinx sees 5 volt tolerance as not useful in their primary 
markets.  The rest of us are just tag alongs in their eyes and don't 
influence their plans.

-- 

Rick

On 3/27/2013 4:55 PM, j.m.granville@gmail.com wrote:
>
> A possible FPGA compromise would be to have one IO bank 5V tolerant, - that would incur the small speed impact in one bank, but users can choose IO and it is rare you need ALL 5V tolerant, or ALL highest speed.

I don't think it is just the speed issue.  I think 5 volt tolerance 
requires a thicker oxide which means separate process steps for the 5 
volt tolerant transistors.  I understand why the FPGA makers do what 
they do.  I just don't like it.

Silicon Blue had the right idea in my opinion.  They were going after a 
market niche for small devices at very low power dissipation.  They felt 
5 volt tolerance was not hard to do in small process geometries and low 
core voltages.  Lattice clearly doesn't feel the need to retain this 
feature considering the costs.  I just wish they would give me some 
packages I can actually use!  0.4 mm BGAs are not very user friendly.

-- 

Rick

On Thursday, March 28, 2013 9:45:55 AM UTC+12, rickman wrote:
> I just wish they would give me some 
> packages I can actually use!  0.4 mm BGAs are not very user friendly.


 Ditto. I cannot understand why they do not have more packages that chase the CPLD business. (eg TQFP48, QFP44 etc )

 -jg

On 3/27/2013 9:23 PM, j.m.granville@gmail.com wrote:
> On Thursday, March 28, 2013 9:45:55 AM UTC+12, rickman wrote:
>> I just wish they would give me some
>> packages I can actually use!  0.4 mm BGAs are not very user friendly.
>
>
>   Ditto. I cannot understand why they do not have more packages that chase the CPLD business. (eg TQFP48, QFP44 etc )

I think it all comes down to volume.  They are targeting the portable 
and cell phone markets where they need to fit the tiniest footprints. 
The rest of us are in the noise...  But once they mature the product 
line perhaps they will come out with a few more packages.

-- 

Rick