8051 - SRAM interface problem

I've successfully interfaced a single 32K SRAM chip to
a T89C51RD2. The CE pin is connected to the A15
line (P2.7) on the 8051.

Happily unencumbered by any real digital design expertise
I decided to piggy-back a second 32K chip (62256) onto
the first one and add an inverter between the two CE lines.
In theory only one of the chips should get selected now.

However, the memory test fails after only a few bytes.
Should this work at all? Any guesses why it's not. The
circuit is assembled on one of those white plastic
breadboards with pluggable wires. The memory chips
are soldered on top of each other. The MC runs at
11 MHz.

Thanks,
Andrew

>I decided to piggy-back a second 32K chip (62256) onto
>the first one and add an inverter between the two CE lines.
>In theory only one of the chips should get selected now.
>

The extra ram is adding to the loading, if you haven't decoupled your power
lines you can get glitchs.

CBarn24050 wrote:

> > I decided to piggy-back a second 32K chip (62256) onto
> > the first one and add an inverter between the two CE lines.
> > In theory only one of the chips should get selected now.
> > 
> 
> The extra ram is adding to the loading, if you haven't decoupled your
> power lines you can get glitchs.

  try a different make for the 373 latch, or HC vs HCT