ADC + FIFO --> IRQ on ISA (or PCI) --> Data Transfer

I'm also trying to design a PC104 (ISA) bus board.

I will interface an ADC (AD9220 or faster) via FIFO buffer to PC104 (ISA)
bus.
I need to control ADC to digitize input signal in a burst and store the
converted data into a FIFO.
When FIFO is full, I need to generate an interrupt to signal the PC104 for
data transfer.
Unfortunatelly I do not have enough experience with CPLD / FPGA (yet).

Is there such a design in public domain showing how to realise such a
system?
Can someone suggest any usefull idea, hint, link, design etc ?

Regards,

k wrote:
> I'm also trying to design a PC104 (ISA) bus board.
> 
> I will interface an ADC (AD9220 or faster) via FIFO buffer to PC104 (ISA)
> bus.
> I need to control ADC to digitize input signal in a burst and store the
> converted data into a FIFO.
> When FIFO is full, I need to generate an interrupt to signal the PC104 for
> data transfer.
> Unfortunatelly I do not have enough experience with CPLD / FPGA (yet).
> 
> Is there such a design in public domain showing how to realise such a
> system?
> Can someone suggest any usefull idea, hint, link, design etc ?
> 


Lewis C Eggebrecht, "Interfacing to the IBM Personal Computer" will get 
you started, though you'll need to look further if you want 16 bit. I 
don't know of any available CPLD implementations, but the circuitry is 
drawn out in the book, so should be easy enough to bash in. IIRC it's 
not very hard.

Paul Burke