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What's the maximum RAM size that can be embedded in an ASIC today?

Started by Unknown August 23, 2013
Hi all,

Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today?

In general, what would be the maximum I could fit, if cost is not a limitation?  Why?

Our need would be for a large number, but could be split into many independent banks if that makes things easier. For example, 1,000 independent banks of 100 MBytes each. 

Or another possible partition (again, if it makes things easier) could be a single huge memory with "normal-size" address bus, say of 20 bits, with a huge data bus of 800,000 bits.  

...Or a mixture of the idea above with the idea of the independent banks.

Thanks so much for your help.

- Juan
Hi Juan,

On 8/23/2013 3:44 PM, juangui.jg@gmail.com wrote:
> Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an > ASIC design today?
Not with your *likely* budget! :> I suspect any fab even thinking about considering your request would push heavily for a hybrid.
> In general, what would be the maximum I could fit, if cost is not a > limitation? Why?
Cost is *always* a limitation. And, cost is *always* a limitation. Furthermore, cost is *always* a limitation. You might try researching the available cores on the market currently. And, pricing an equivalent amount of COTS memory (with "whatever" other specifications you haven't mentioned). Then, ask yourself if you plan on buying in the same sorts of quantities that this COTS memory is currently produced/sold. If *not*, consider how willing a fab will be to tie up their resources for the quantities *you* want -- as an "exclusive" customer.
> Our need would be for a large number, but could be split into many > independent banks if that makes things easier. For example, 1,000 > independent banks of 100 MBytes each.
Is there some OVERWHELMING REASON why you couldn't locate the store *outside* the ASIC and take advantage of *commodity* memory to give you that capacity? E.g., even if it means you have to think a bit harder on your problem and implement some caching internal/external to the ASIC? ("Think smarter")
> Or another possible partition (again, if it makes things easier) could > be a single huge memory with "normal-size" address bus, say of 20 bits, > with a huge data bus of 800,000 bits. > > ....Or a mixture of the idea above with the idea of the independent banks. > > Thanks so much for your help.
On 8/23/2013 6:44 PM, juangui.jg@gmail.com wrote:
> Hi all, > > Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today? > > In general, what would be the maximum I could fit, if cost is not a limitation? Why? > > Our need would be for a large number, but could be split into many independent banks if that makes things easier. For example, 1,000 independent banks of 100 MBytes each. > > Or another possible partition (again, if it makes things easier) could be a single huge memory with "normal-size" address bus, say of 20 bits, with a huge data bus of 800,000 bits. > > ...Or a mixture of the idea above with the idea of the independent banks. > > Thanks so much for your help.
An interesting question. Bu the way you put it, if cost is not the limiting factor, what is? Does it have to be currently available? Does it have to fit on a chip of a given size? If you place no constraints on the problem, you end up with an unconstrained answer. -- Rick
On Fri, 23 Aug 2013 15:44:33 -0700 (PDT), juangui.jg@gmail.com wrote:

>Hi all, > >Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today? > >In general, what would be the maximum I could fit, if cost is not a limitation? Why? > >Our need would be for a large number, but could be split into many independent banks if that makes things easier. For example, 1,000 independent banks of 100 MBytes each. > >Or another possible partition (again, if it makes things easier) could be a single huge memory with "normal-size" address bus, say of 20 bits, with a huge data bus of 800,000 bits. > >...Or a mixture of the idea above with the idea of the independent banks. > >Thanks so much for your help.
You can get roughly 4Gb of DRAM on a 40mm**2 die these days. The biggest logic/memory die, reticle limited, you can make, is about 600mm**2 (that can be pushed a bit). So call it somewhere in the 60Gb range (7.5GB) , give or take. At that size you'd better leave a chunk for redundancy though (further reducing capacity), since you defect density will otherwise kill you. Several option including stacking dies in a package, wafer scale integration, or some other sort of MCM technology (whether that counts depends on your definition of ASIC). Alternatively, you could pay (if cost is really no object) to develop new steppers and whatnot with bigger reticle limits. Just be sure to bring your eleven figure bank balance.
In article <7e45c191-bf06-4987-80e3-fd222792bb34@googlegroups.com>, 
juangui.jg@gmail.com says...
> > Hi all, > > Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today?
So you want to put a Hard Drive on a single ASIC, or bank of ASICs?
> In general, what would be the maximum I could fit, if cost is not a limitation? Why? > > Our need would be for a large number, but could be split into many independent banks if that makes things easier. For example, 1,000 independent banks of 100 MBytes each.
That much data which has time limits to fill or read the whole lot, in RAM as data that is volatile. Means if that really is the case you dont care if power fails and loss of data; even if the whole system has has all sorts of multiple power sources, there are always situations where power is removed from maintenance to fire in building. Suggests a tiny market, suggests tiny volumes, so unless you have a govt agency funding design you would never afford it or get it built.
> Or another possible partition (again, if it makes things easier) could be a single huge memory with "normal-size" address bus, say of 20 bits, with a huge data bus of 800,000 bits. > > ...Or a mixture of the idea above with the idea of the independent banks.
Wonders if you want a disk drive size data why you dont use disk drive methods or methods in parallel and/or caching to solve the issue. Or simply use hard drive(s) anyway.
> Thanks so much for your help. > > - Juan
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On Fri, 23 Aug 2013 15:44:33 -0700 (PDT), juangui.jg@gmail.com wrote:

>Or another possible partition (again, if it makes things easier) could be a single huge memory with "normal-size" address bus, say of 20 bits, with a huge data bus of 800,000 bits.
Assuming 64 Gib with current technology mentioned in an other message, using a rectangular organization would be 256 Krows x 256 Kcolumns, thus an 18 bit row address would be needed and 256 K column sense amplifiers/latches effectively creating a 32 KiB cache line, thus eliminating much of the bottleneck caused by having a narrow (64-128 bit) multiplexed external data bus
>...Or a mixture of the idea above with the idea of the independent banks.
That is a real issue how to handle cache collisions. While the memory array could be a single plane, after the column amplifiers, there must be multiple cache lines, at least one for code and an other for data, in practice much more. Since code is more or less sequential, it would benefit from long cache lines, also using very long instruction words would be attractive, each bit could control directly some data path switching. It is more problematic with data, how do you shuffle in and out huge amount of data. Using 9 KB Ethernet Jumbo frames, it would take more than three frames to fill the cache line. At 10 Gbit/s Ethernet a Jumbo frame takes 7 us or 140 Kframes/s. So in order to utilize th full capacity of such memory architecture, you would need a lot of external I/O connections. So something like a 32 port 10 Gbit/s ethernet switch might be a possible application.
> In general, what would be the maximum I could fit, if cost is not a limitation? Why?
I love answering these no-cost-limitation questions. :) There is no limit to how much RAM you can fit onto an ASIC if cost is not a constraint. It's your money and you can spend as much of it as you want. JJS
On 2013-08-26, John Speth <johnspeth@yahoo.com> wrote:

>> In general, what would be the maximum I could fit, if cost is not a >> limitation? Why? > > I love answering these no-cost-limitation questions. :) > > There is no limit to how much RAM you can fit onto an ASIC if cost is > not a constraint.
Indeed. If current fabs and wafer-processing tools are a limit, then with unlimited funds you can build your own fab, make your own tools, and develop your own fancy new 4D transistor geometries, electron-spin-cells, or sub-atomc-size black holes to be used as memory elements. -- Grant Edwards grant.b.edwards Yow! The PILLSBURY DOUGHBOY at is CRYING for an END to gmail.com BURT REYNOLDS movies!!
In comp.arch.embedded,
Grant Edwards <invalid@invalid.invalid> wrote:
> On 2013-08-26, John Speth <johnspeth@yahoo.com> wrote: > >>> In general, what would be the maximum I could fit, if cost is not a >>> limitation? Why? >> >> I love answering these no-cost-limitation questions. :) >> >> There is no limit to how much RAM you can fit onto an ASIC if cost is >> not a constraint. > > Indeed. If current fabs and wafer-processing tools are a limit, then > with unlimited funds you can build your own fab, make your own tools, > and develop your own fancy new 4D transistor geometries, > electron-spin-cells, or sub-atomc-size black holes to be used as > memory elements.
The post's subject puts a huge constraint on approaches like that: It has to happen today. Don't know where the OP lives, but over here there's under 40 minutes left to do it. So the correct answer will be a lot closer to zero that the numbers I've seen so far. :-) -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) "Why must you tell me all your secrets when it's hard enough to love you knowing nothing?" -- Lloyd Cole and the Commotions
On 2013-08-26, Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote:
> In comp.arch.embedded, > Grant Edwards <invalid@invalid.invalid> wrote: >> On 2013-08-26, John Speth <johnspeth@yahoo.com> wrote: >> >>>> In general, what would be the maximum I could fit, if cost is not a >>>> limitation? Why? >>> >>> I love answering these no-cost-limitation questions. :) >>> >>> There is no limit to how much RAM you can fit onto an ASIC if cost is >>> not a constraint. >> >> Indeed. If current fabs and wafer-processing tools are a limit, then >> with unlimited funds you can build your own fab, make your own tools, >> and develop your own fancy new 4D transistor geometries, >> electron-spin-cells, or sub-atomc-size black holes to be used as >> memory elements. > > The post's subject puts a huge constraint on approaches like that: > It has to happen today.
Ah, I completely missed that.
> Don't know where the OP lives, but over here there's under 40 minutes > left to do it. So the correct answer will be a lot closer to zero that > the numbers I've seen so far. :-)
I've survived about a half-dozen ASIC efforts, and you're right: you can't do anything today. Nor can you do anything this month or this quarter. In my experience it's pretty much always to late to do do anything this year. Next year may or may not be possible... -- Grant Edwards grant.b.edwards Yow! Zippy's brain cells at are straining to bridge gmail.com synapses ...