Forums

LAN91C111Internal PHY

Started by Ted Wood March 19, 2004
We're having a problem getting the SMSC LAN91C111 to work on one of
our ColdFire boards. We can access memory-mapped MAC registers, but we
can't get the serial Management Interface to the PHY to work.
Selecting the external PHY connection to break our MI signals out,
everything looks fine on the scope, right number of clock pulses etc.,
etc.

Am I missing something obvious?

Cheers
TW
"Ted Wood" <tedwood@ornette.freeserve.co.uk> wrote in message
news:7eb49faa.0403190928.4870237c@posting.google.com...
> We're having a problem getting the SMSC LAN91C111 to work on one of > our ColdFire boards. We can access memory-mapped MAC registers, but we > can't get the serial Management Interface to the PHY to work. > Selecting the external PHY connection to break our MI signals out, > everything looks fine on the scope, right number of clock pulses etc., > etc. > > Am I missing something obvious? >
Check that the MII serial clock is slow enough, and that there are good setup and hold times around the active clock edge. An ARM7TDMI at 50 MHz was too quick before slowing down. Did you remember to wake the MII up? It is disabled after HW reset. HTH Tauno Voipio tauno voipio @ iki fi
"Tauno Voipio" <tauno.voipio@iki.fi.SPAMBAIT_REMOVE.invalid> schrieb im
Newsbeitrag news:32H6c.368$_p.339@read3.inet.fi...
> > "Ted Wood" <tedwood@ornette.freeserve.co.uk> wrote in message > news:7eb49faa.0403190928.4870237c@posting.google.com... > > We're having a problem getting the SMSC LAN91C111 to work on one of > > our ColdFire boards. We can access memory-mapped MAC registers, but we > > can't get the serial Management Interface to the PHY to work. > > Selecting the external PHY connection to break our MI signals out, > > everything looks fine on the scope, right number of clock pulses etc., > > etc. > > > > Am I missing something obvious? > > > > Check that the MII serial clock is slow enough, and that there are > good setup and hold times around the active clock edge. An ARM7TDMI > at 50 MHz was too quick before slowing down. > > Did you remember to wake the MII up? It is disabled after HW reset.
Also check that the 32 preamble bits are present. Max. MII is 2.5MHz if I remember correctly. - Rene
"Rene" <spam@see5.ch> wrote in message news:<405cc028$0$721$5402220f@news.sunrise.ch>...

> > > > Did you remember to wake the MII up? It is disabled after HW reset.
We're enabling it via the MAC bit. Is there anyhting else that needs to be done? TW
Ted Wood wrote:
> "Rene" <spam@see5.ch> wrote in message news:<405cc028$0$721$5402220f@news.sunrise.ch>... > > >>>Did you remember to wake the MII up? It is disabled after HW reset. > > > We're enabling it via the MAC bit. Is there anyhting else that needs to be done? > TW
Send first MII reset to physical control register, then wait at least 50 milliseconds *without attempting to access the MII*, then write autonegotiation enable and autonegotiation reset to the same register. If everything succeeds, you should get the link up within about a second. HTH Tauno Voipio tauno voipio @ iki fi