Hello ! We are an academic institution teaching our students VLSI design, from FPGA to full custom ASIC. We have put great value on teaching VHDL during the past years with very good results from our students. However, we have the impression that these students have difficulties working with schematics as tools to document and express their architectural ideas, in part because we did not provide them with such a schematic edition tool and thus, we are currently thinking about adding such a tool to our design flow. Among the requirements that we have collected for such a tool would be: - real schematic edition tool, and not just a drawing tool, i.e: - recognizes and keep the connectivity - understands connectors and inversion bubbles - can select whole nets and name them - is able to work with hierarchical schematics - makes a graphic difference between scalars and vectors (buses) - available for different plattforms: Wintel, Linux, Mac OSX - from the cost viewpoint, affordable by students, i.e: no high-end tool - a library with block level (adder, multiplier, ALU, registers, datapath elements, memory, etc.) symbols is available, or can easily be buit. - the tool must be able to netlist any schematic hierarchy into a VHDL skeleton with entities declaration, instantiation statements and architecture templates so that it support the VHDL code writing. Any suggestions? Fran
Schematic Edition Tool : Suggestions
Started by ●March 16, 2004
Reply by ●March 16, 20042004-03-16
"Francisco Camarero" <nospam@nospam.com> wrote in message news:4056A867.9351BC4D@nospam.com...> However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be:(...)> Any suggestions?EagleCAD? It does not fulfill all your needs but it's free (small version suitable for students) and scalable to a full-blown system. Unfortunately it can't easily handle transition to logic/FPGA.
Reply by ●March 16, 20042004-03-16
<snip>> Any suggestions?Haven't checked if it fulfills all your requirements but maybe this would help: http://www.expressivesystems.com/ --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.622 / Virus Database: 400 - Release Date: 14/03/2004
Reply by ●March 16, 20042004-03-16
"Francisco Camarero" <nospam@nospam.com> wrote in message news:4056A867.9351BC4D@nospam.com...> > > Hello ! > > We are an academic institution teaching our students VLSI design, fromFPGA> to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > FranThere are some integrated schematic and VHDL tools that come with the free Xilinx ISE web edition and free versions of Altera Quartus.
Reply by ●March 16, 20042004-03-16
Have a look at www.expressivesystems.com this tool is used by a few European Uni's to teach language based design. Regards, Steve Francisco Camarero <nospam@nospam.com> wrote in message news:<4056A867.9351BC4D@nospam.com>...> Hello ! > > We are an academic institution teaching our students VLSI design, from FPGA > to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > Fran
Reply by ●March 16, 20042004-03-16
The Quartus product from Altera will suit your needs, and includes a schematic editor with netlisting capabilities.. The Quartus design entry system allows you to mix and match VHDL, Verilog and Schematics. The product however does not support the MacOS, but will meet all the other requirements, and is widely used by universities today. The built in text editor has support for HDL language templates, and the language parser has good error location capabilities into the Text Editor. More information about the University program can be found at: http://www.altera.com/education/univ/unv-index.html A free version of the Tool can be downloaded at: http://www.altera.com/education/univ/software/unv-software.html - Subroto Datta Altera Corp. "Francisco Camarero" <nospam@nospam.com> wrote in message news:4056A867.9351BC4D@nospam.com...> > > Hello ! > > We are an academic institution teaching our students VLSI design, fromFPGA> to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > Fran
Reply by ●March 16, 20042004-03-16
"Francisco Camarero" <nospam@nospam.com> wrote in message news:4056A867.9351BC4D@nospam.com...> > > Hello ! > > We are an academic institution teaching our students VLSI design, fromFPGA> to full custom ASIC. We have put great value on teaching VHDL during the > past years with very good results from our students. > > However, we have the impression that these students have difficulties > working with schematics as tools to document and express their > architectural ideas, in part because we did not provide them with such a > schematic edition tool and thus, we are currently thinking about adding > such a tool to our design flow. > > Among the requirements that we have collected for such a tool would be: > > - real schematic edition tool, and not just a drawing tool, i.e: > - recognizes and keep the connectivity > - understands connectors and inversion bubbles > - can select whole nets and name them > - is able to work with hierarchical schematics > - makes a graphic difference between scalars and vectors (buses) > > - available for different plattforms: Wintel, Linux, Mac OSX > > - from the cost viewpoint, affordable by students, i.e: no high-end tool > > - a library with block level (adder, multiplier, ALU, registers, datapath > elements, memory, etc.) symbols is available, or can easily be buit. > > - the tool must be able to netlist any schematic hierarchy into a VHDL > skeleton with entities declaration, instantiation statements and > architecture templates so that it support the VHDL code writing. > > Any suggestions? > > > FranThe best of both worlds is to do all the design in HDL, and then use a tool like Synplify's "HDL Analyst" to look at a schematic version of the synthesized code. Using Synplify one can see either the RTL or structural schematic. -Kevin
Reply by ●March 16, 20042004-03-16
Subroto Datta wrote:>... snip ...> > A free version of the Tool can be downloaded at: > http://www.altera.com/education/univ/software/unv-software.htmlNo it can't. That page says, in part: "Contact your University Program liaison to obtain copies of these programs and a license to use them. You must be a student, professor, or university staff member of a university that is a member of the Altera University program." and please do not toppost. -- Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net> USE worldnet address!
Reply by ●March 16, 20042004-03-16
"Kevin Neilson" wrote:> The best of both worlds is to do all the design in HDL, and then use a tool > like Synplify's "HDL Analyst" to look at a schematic version of the > synthesized code. Using Synplify one can see either the RTL or structural > schematic.I agree with Kevin. It is a good thing to look at the rtl/netlist schematics. But let the computer draw them for you. Note that QuartusII ver 4.0 also includes an rtl viewer. -- Mike Treseler
Reply by ●March 16, 20042004-03-16
CBFalconer <cbfalconer@yahoo.com> wrote in message news:<4057371F.6364CB4F@yahoo.com>...> Subroto Datta wrote: > > > ... snip ... > > > > A free version of the Tool can be downloaded at: > > http://www.altera.com/education/univ/software/unv-software.html > > No it can't. That page says, in part: > > "Contact your University Program liaison to obtain copies of these > programs and a license to use them. You must be a student, > professor, or university staff member of a university that is a > member of the Altera University program." > > and please do not toppost.Hello CB, The web page has a link to the Quartus Web Edition which is FREE, and does not require you to be a student, preofessor or university student :-) - Subroto Datta Altera Corp.
