ASIC development question

Hey folks,
   I am working on a project where our cost and size
are creeping up and some of our management are starting
to ask about whether or not we need to be considering
going to ASIC technology.  Fortunately, our budget allows
us to consider this option.

   Since I have never been in charge of a project that designed
its own chip, I have a few Q's that I hope the embedded
folks can help me with:

1)  If we want to hire consultants or specialists in this area,
     what is the best way to go about doing it?

2)  What is the design process for one of these beasts?  Is it
     similar to other embedded projects?

3)  What tools would we have to buy to design our chip?

4)  How do you predict the design time?

5)  How are the ASICs priced in production?

Sorry for the beginner ASIC questions...any insight or pointers
will be helpful...thanks,

--Keith Brafford

Hey folks,
   I am working on a project where our cost and size
are creeping up and some of our management are starting
to ask about whether or not we need to be considering
going to ASIC technology.  Fortunately, our budget allows
us to consider this option.

   Since I have never been in charge of a project that designed
its own chip, I have a few Q's that I hope the embedded
folks can help me with:

1)  If we want to hire consultants or specialists in this area,
     what is the best way to go about doing it?

2)  What is the design process for one of these beasts?  Is it
     similar to other embedded projects?

3)  What tools would we have to buy to design our chip?

4)  How do you predict the design time?

5)  How are the ASICs priced in production?

Sorry for the beginner ASIC questions...any insight or pointers
will be helpful...thanks,

--Keith Brafford

Keith Brafford wrote:
> Hey folks,
>    I am working on a project where our cost and size
> are creeping up and some of our management are starting
> to ask about whether or not we need to be considering
> going to ASIC technology.  Fortunately, our budget allows
> us to consider this option.
> 
>    Since I have never been in charge of a project that designed
> its own chip, I have a few Q's that I hope the embedded
> folks can help me with:
> 
> 1)  If we want to hire consultants or specialists in this area,
>      what is the best way to go about doing it?
> 
> 2)  What is the design process for one of these beasts?  Is it
>      similar to other embedded projects?

It can be, ever done a MASK ROM spin ?

> 
> 3)  What tools would we have to buy to design our chip?
> 
> 4)  How do you predict the design time?

You _do_ have something that works now, that management have
signed off on ?

> 
> 5)  How are the ASICs priced in production?

Depends.
Normally, you are responsible for all testing and Yield that is not
process specific.
Just defining where the line is drawn, and what is a pass/fail,
is non trival.

> Sorry for the beginner ASIC questions...any insight or pointers
> will be helpful...thanks,

Look at WHY you think you need an ASIC very carefully.
If it is size, what about Known Good Die, smaller packages... ?
If it is cost, don't expect radical savings - more of a cost transference.
Can it _really_ not be solved with the right mix of standard devices...

Another very important point to define, is where does ASIC_#2 fit.
  Often, getting resource for the first one, is easier than the
second one - and the second one may be important downstream.

If you can morph your ASIC into a masked gatearray, then you can
do a lot of testing and proving using std FPGAs, then take your
design ( which will be in production ) to the vendors who specialise
in FPGA -> ASIC flows.

-jg

Keith Brafford <kbrafford@nospam.earthlink.net> wrote:

[...]
> 2)  What is the design process for one of these beasts?  Is it
>      similar to other embedded projects?

Similar to _some_ embedded projects, yes, but not to all of them.  It
depends on what you've done so far.

> 3)  What tools would we have to buy to design our chip?

Essentially the same used for FPGA / CPLD designs.  But with a *lot*
more testing and simulation before you can risk to have actual
prototypes made.

> 4)  How do you predict the design time?

How others do it is irrelevant.  It's just too dependant on your
shop's level of experience with this type of work for anybody else's
predictions to be anywhere near reliable for your projects.

> 5)  How are the ASICs priced in production?

Ouch.  If you don't already know that, whatever gave you the idea that
ASICs might be a way out of your problem?

This shows massive symptoms of a PHB initiative.

-- 
Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.

"Keith Brafford" <kbrafford@NOSPAM.earthlink.net> wrote in message news:<30T3c.32860$aT1.127@newsread1.news.pas.earthlink.net>...
> Hey folks,
>    I am working on a project where our cost and size
> are creeping up and some of our management are starting
> to ask about whether or not we need to be considering
> going to ASIC technology.  Fortunately, our budget allows
> us to consider this option.
> 
>    Since I have never been in charge of a project that designed
> its own chip, I have a few Q's that I hope the embedded
> folks can help me with:
> 
> 1)  If we want to hire consultants or specialists in this area,
>      what is the best way to go about doing it?

Don't try to do it all in house. Do as much of the design work in
FPGAs, then hand it over to someone that will turn in in to an ASIC.

> 3)  What tools would we have to buy to design our chip?

Lots. About $1m worth. Better to pay someone else to do the work.
Expect to pay $30-100k depending on how complex it is.
 
> 4)  How do you predict the design time?

Start at a year and work up. All depends on what you're trying to
design really.

> 5)  How are the ASICs priced in production?

You pay a couple of hundred thousand for mask costs, then a couple of
thousand for each wafer. You then need to add on to that test and
packaging costs.

Have you considered structured ASICs / gate-arrays. Kind of a half-way
house between FPGAs and ASICs. All depends on your volumes really..
 
Cheers,
JonB

"Keith Brafford" <kbrafford@NOSPAM.earthlink.net> wrote in message
news:30T3c.32860$aT1.127@newsread1.news.pas.earthlink.net...
> Hey folks,
>    I am working on a project where our cost and size
> are creeping up and some of our management are starting
> to ask about whether or not we need to be considering
> going to ASIC technology.  Fortunately, our budget allows
> us to consider this option.
>
>    Since I have never been in charge of a project that designed
> its own chip, I have a few Q's that I hope the embedded
> folks can help me with:
>
> 1)  If we want to hire consultants or specialists in this area,
>      what is the best way to go about doing it?

You may try post some messages and information on your particular design to
the comp.arch.fpga...The HDL geeks over there can give you better response
than embedded engineers here...

>
> 2)  What is the design process for one of these beasts?  Is it
>      similar to other embedded projects?

This is a complicated process. Starting with C/Matlab simulation,
discretization and optimization,
2ndly you will do hardware/software partitioning, 3rdly you will code the
finished hardware design in
HDL (Verilog/VHDL) for simulation & synthesis. Lastly, you send in the
synthesized design for place
& route, mask creation, packaging.

Alternatively, if you are familiar with embedded design, you may consider
http://www.celoxica.com/
for their Handel-C, which 'compiles' specialized C constructs into hardware
for evaluation on an FPGA.

>
> 3)  What tools would we have to buy to design our chip?

You need at least a Design Compiler from Synopsys if you intend to design it
in house, which is used
for HDL synthesis, and a HDL simulator, e.g. Model-sim, Verilog-XL, etc.
Place & route is usually
out-sourced to third party companies.

>
> 4)  How do you predict the design time?

Depending on the complexity of your design and the process, the time could
range from 9 months to years.

>
> 5)  How are the ASICs priced in production?

ASICs are costy, especially when the gate size goes down. However, if your
design doesn't require
the kind of speed & power as a Pentium 3 processor, consider out-source the
design to China and
Indian. They have older processes and cheap engineers.

>
> Sorry for the beginner ASIC questions...any insight or pointers
> will be helpful...thanks,
>
> --Keith Brafford
>
>
>
>
>
>

"Keith Brafford" <kbrafford@NOSPAM.earthlink.net> skrev i meddelandet
news:30T3c.32860$aT1.127@newsread1.news.pas.earthlink.net...
> Hey folks,
>    I am working on a project where our cost and size
> are creeping up and some of our management are starting
> to ask about whether or not we need to be considering
> going to ASIC technology.  Fortunately, our budget allows
> us to consider this option.
>
>    Since I have never been in charge of a project that designed
> its own chip, I have a few Q's that I hope the embedded
> folks can help me with:
>
> 1)  If we want to hire consultants or specialists in this area,
>      what is the best way to go about doing it?
>
> 2)  What is the design process for one of these beasts?  Is it
>      similar to other embedded projects?

One possible route is to design an FPGA and then do a
translation to a hardwired FPGA like the Atmel ULC program (There are others
that will do this of course).
Provide FPGA design data and testvectors and the ASIC work is done by your
friendly vendor.
If the resulting ASIC meets the testvectors, you have approved the part and
the
lorries with component should start arriving in a few months.
Typically, you need to commit to business around 500k-1M$ per year.

Another route if you dont have the experience, is to let the semiconductor
vendor
design it for you according to your specification.
Again commitment of some kind is needed.


>
> 3)  What tools would we have to buy to design our chip?
>
> 4)  How do you predict the design time?
>
> 5)  How are the ASICs priced in production?
>
> Sorry for the beginner ASIC questions...any insight or pointers
> will be helpful...thanks,
>
> --Keith Brafford
>
>



-- 
Best Regards,
Ulf Samuelsson   ulf@a-t-m-e-l.com
This is a personal view which may or may not be
share by my Employer Atmel Nordic AB