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Opensource Debugging Model Question

Started by Randy Yates May 23, 2014
I am curious how this works at the register level. I am going by the
description here, especially the graphic showing the flow and interfaces
of the debugging model.

http://mcuoneclipse.com/2013/07/22/diy-free-toolchain-for-kinetis-part-3-debugger-gdb-server-with-pe-and-segger/

So my question is, when you're in debugging mode, how does Eclipse
"know" what registers comprise the target? Is this information somehow
provided by the GDB server?

Related: how does an Eclipse debugging session "know" what peripherals
are on the specific target chip you're debugging? For example, would it
be able to know that one version of Freescale Kinetis has 2 I2C
interfaces while another has 3 (hypothetically)?
-- 
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com
Randy Yates <yates@digitalsignallabs.com> writes:

> I am curious how this works at the register level. I am going by the > description here, especially the graphic showing the flow and interfaces > of the debugging model. > > http://mcuoneclipse.com/2013/07/22/diy-free-toolchain-for-kinetis-part-3-debugger-gdb-server-with-pe-and-segger/ > > So my question is, when you're in debugging mode, how does Eclipse > "know" what registers comprise the target? Is this information somehow > provided by the GDB server? > > Related: how does an Eclipse debugging session "know" what peripherals > are on the specific target chip you're debugging? For example, would it > be able to know that one version of Freescale Kinetis has 2 I2C > interfaces while another has 3 (hypothetically)?
And to know, e.g., what the base addresses of those peripherals are and to be able to display in "decoded" form the peripheral registers (e.g., the Master/Slave bit in an I2C peripheral)? -- Randy Yates Digital Signal Labs http://www.digitalsignallabs.com
On 23.5.14 16:30, Randy Yates wrote:
> I am curious how this works at the register level. I am going by the > description here, especially the graphic showing the flow and interfaces > of the debugging model. > > http://mcuoneclipse.com/2013/07/22/diy-free-toolchain-for-kinetis-part-3-debugger-gdb-server-with-pe-and-segger/ > > So my question is, when you're in debugging mode, how does Eclipse > "know" what registers comprise the target? Is this information somehow > provided by the GDB server?
The target (core) processor registers are known by GDB. Eclipse works here as a polished front-end to GDB.
> Related: how does an Eclipse debugging session "know" what peripherals > are on the specific target chip you're debugging? For example, would it > be able to know that one version of Freescale Kinetis has 2 I2C > interfaces while another has 3 (hypothetically)?
In the setup of the link, the peripherals and the board around the core processor are known by the P&E debugger interface module. There are many similarly functioning modules for Eclipse around, for several different chips and even boards. P&E have provided debuggers for Motorola/Freescale for a long time. I may still have somewhere a P&E dongle for MC68332. -- Tauno Voipio
Tauno Voipio <tauno.voipio@notused.fi.invalid> writes:

> On 23.5.14 16:30, Randy Yates wrote: >> I am curious how this works at the register level. I am going by the >> description here, especially the graphic showing the flow and interfaces >> of the debugging model. >> >> http://mcuoneclipse.com/2013/07/22/diy-free-toolchain-for-kinetis-part-3-debugger-gdb-server-with-pe-and-segger/ >> >> So my question is, when you're in debugging mode, how does Eclipse >> "know" what registers comprise the target? Is this information somehow >> provided by the GDB server? > > The target (core) processor registers are known by GDB. > Eclipse works here as a polished front-end to GDB. > >> Related: how does an Eclipse debugging session "know" what peripherals >> are on the specific target chip you're debugging? For example, would it >> be able to know that one version of Freescale Kinetis has 2 I2C >> interfaces while another has 3 (hypothetically)? > > > In the setup of the link, the peripherals and the board around > the core processor are known by the P&E debugger interface module. > > There are many similarly functioning modules for Eclipse around, > for several different chips and even boards. > > P&E have provided debuggers for Motorola/Freescale for a long > time. I may still have somewhere a P&E dongle for MC68332.
Thanks Tauno. Actually I was planning on going with Segger's J-Link Pro and their corresponding GDB server, http://www.segger.com/jlink-gdb-server.html but I guess the answer is the same. So you're saying it is somehow dynamically defined by the GDB client/server interface, which is what I thought. -- Randy Yates Digital Signal Labs http://www.digitalsignallabs.com
On 23.5.14 23:33, Randy Yates wrote:
> Tauno Voipio <tauno.voipio@notused.fi.invalid> writes: > >> On 23.5.14 16:30, Randy Yates wrote: >>> I am curious how this works at the register level. I am going by the >>> description here, especially the graphic showing the flow and interfaces >>> of the debugging model. >>> >>> http://mcuoneclipse.com/2013/07/22/diy-free-toolchain-for-kinetis-part-3-debugger-gdb-server-with-pe-and-segger/ >>> >>> So my question is, when you're in debugging mode, how does Eclipse >>> "know" what registers comprise the target? Is this information somehow >>> provided by the GDB server? >> >> The target (core) processor registers are known by GDB. >> Eclipse works here as a polished front-end to GDB. >> >>> Related: how does an Eclipse debugging session "know" what peripherals >>> are on the specific target chip you're debugging? For example, would it >>> be able to know that one version of Freescale Kinetis has 2 I2C >>> interfaces while another has 3 (hypothetically)? >> >> >> In the setup of the link, the peripherals and the board around >> the core processor are known by the P&E debugger interface module. >> >> There are many similarly functioning modules for Eclipse around, >> for several different chips and even boards. >> >> P&E have provided debuggers for Motorola/Freescale for a long >> time. I may still have somewhere a P&E dongle for MC68332. > > Thanks Tauno. Actually I was planning on going with Segger's J-Link > Pro and their corresponding GDB server, > > http://www.segger.com/jlink-gdb-server.html > > but I guess the answer is the same. > > So you're saying it is somehow dynamically defined by the GDB > client/server interface, which is what I thought.
The GDB is run from Eclipse, instead of the console. The Segger box (or some other similar tool, P&E, OpenOCD etc) runs as a GDB remote processor agent, and it is able to feed information to the GDB. It is a private matter of the interface box and the target processor / board how the communication in the last leg is handled. Both the console control protocols and the remote agent protocol are well described in the GDB documentation. Another way to describe the interface registers to the debugger is to write a struct of the registers of a peripheral, and make its address public to the linker. There are two ways: either to use an assembler module with the absolute addresses as public symbols, or feeding the addresses via the linker script. I'm using the assembly language module method with GCC, GDB and OpenOCD, for ARM7TDMI, Cortex-M3 and Cortex-M4. -- -Tauno