Forums

FPGA on Android

Started by Tim December 1, 2014
- non-volatile FPGA plus FTDI USB chip
- connects to an Android host mode USB port
- application software in Lua, with Java interface/driver
- high-level Gideros software for whizzy graphics
- FPGA firmware samples, including logic analyzer in source

also works on a PC - useful for reprogramming the FPGA.

Everything open source.

www.bugblat.com/products/fan

--
Tim
On 01/12/2014 14:30, Tim wrote:
> - non-volatile FPGA plus FTDI USB chip > - connects to an Android host mode USB port > - application software in Lua, with Java interface/driver > - high-level Gideros software for whizzy graphics > - FPGA firmware samples, including logic analyzer in source > > also works on a PC - useful for reprogramming the FPGA. > > Everything open source. > > www.bugblat.com/products/fan > > -- > Tim
Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I think I'll buy one. I'm really pleased to see the open source, VHDL, LUA and Android host - nice combination. Michael Kellett
On 02/12/2014 09:20, MK wrote:
> On 01/12/2014 14:30, Tim wrote: >> - non-volatile FPGA plus FTDI USB chip >> - connects to an Android host mode USB port >> - application software in Lua, with Java interface/driver >> - high-level Gideros software for whizzy graphics >> - FPGA firmware samples, including logic analyzer in source >> >> also works on a PC - useful for reprogramming the FPGA. >> >> Everything open source. >> >> www.bugblat.com/products/fan >> >> -- >> Tim > Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I > think I'll buy one. > I'm really pleased to see the open source, VHDL, LUA and Android host - > nice combination. > > Michael Kellett
The ICE40 non-volatile memory is OTP. You can also program the SRAM directly, but OTP is a problem in some applications. And this board is a spin-off from a bigger project, for which the XO2 is the best fit.
On 12/3/2014 11:39 AM, Tim wrote:
> On 02/12/2014 09:20, MK wrote: >> On 01/12/2014 14:30, Tim wrote: >>> - non-volatile FPGA plus FTDI USB chip >>> - connects to an Android host mode USB port >>> - application software in Lua, with Java interface/driver >>> - high-level Gideros software for whizzy graphics >>> - FPGA firmware samples, including logic analyzer in source >>> >>> also works on a PC - useful for reprogramming the FPGA. >>> >>> Everything open source. >>> >>> www.bugblat.com/products/fan >>> >>> -- >>> Tim >> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I >> think I'll buy one. >> I'm really pleased to see the open source, VHDL, LUA and Android host - >> nice combination. >> >> Michael Kellett > > The ICE40 non-volatile memory is OTP. You can also program the SRAM > directly, but OTP is a problem in some applications. > > And this board is a spin-off from a bigger project, for which the XO2 is > the best fit.
Does the board have support for measuring power consumption of the XO2? Different rails? -- Rick
On 03/12/2014 21:52, rickman wrote:
> On 12/3/2014 11:39 AM, Tim wrote: >> On 02/12/2014 09:20, MK wrote: >>> On 01/12/2014 14:30, Tim wrote: >>>> - non-volatile FPGA plus FTDI USB chip >>>> - connects to an Android host mode USB port >>>> - application software in Lua, with Java interface/driver >>>> - high-level Gideros software for whizzy graphics >>>> - FPGA firmware samples, including logic analyzer in source >>>> >>>> also works on a PC - useful for reprogramming the FPGA. >>>> >>>> Everything open source. >>>> >>>> www.bugblat.com/products/fan >>>> >>>> -- >>>> Tim >>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I >>> think I'll buy one. >>> I'm really pleased to see the open source, VHDL, LUA and Android host - >>> nice combination. >>> >>> Michael Kellett >> >> The ICE40 non-volatile memory is OTP. You can also program the SRAM >> directly, but OTP is a problem in some applications. >> >> And this board is a spin-off from a bigger project, for which the XO2 is >> the best fit. > > Does the board have support for measuring power consumption of the XO2? > Different rails? >
There's only one rail - 3.3V. This flavor of the XO2 has an internal regulator for the core voltage. You can measure current draw by one of - a USB current meter, easy to find on eBay - lift the Schottky in the power input and replace with a 0.1R resistor. As always, current consumption in an FPGA depends on the design it is programmed with. But you know that. --- Tim
On 12/3/2014 6:25 PM, Tim wrote:
> On 03/12/2014 21:52, rickman wrote: >> On 12/3/2014 11:39 AM, Tim wrote: >>> On 02/12/2014 09:20, MK wrote: >>>> On 01/12/2014 14:30, Tim wrote: >>>>> - non-volatile FPGA plus FTDI USB chip >>>>> - connects to an Android host mode USB port >>>>> - application software in Lua, with Java interface/driver >>>>> - high-level Gideros software for whizzy graphics >>>>> - FPGA firmware samples, including logic analyzer in source >>>>> >>>>> also works on a PC - useful for reprogramming the FPGA. >>>>> >>>>> Everything open source. >>>>> >>>>> www.bugblat.com/products/fan >>>>> >>>>> -- >>>>> Tim >>>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA >>>> but I >>>> think I'll buy one. >>>> I'm really pleased to see the open source, VHDL, LUA and Android host - >>>> nice combination. >>>> >>>> Michael Kellett >>> >>> The ICE40 non-volatile memory is OTP. You can also program the SRAM >>> directly, but OTP is a problem in some applications. >>> >>> And this board is a spin-off from a bigger project, for which the XO2 is >>> the best fit. >> >> Does the board have support for measuring power consumption of the XO2? >> Different rails? >> > > There's only one rail - 3.3V. This flavor of the XO2 has an internal > regulator for the core voltage. > > You can measure current draw by one of > - a USB current meter, easy to find on eBay > - lift the Schottky in the power input and replace with a 0.1R resistor.
There is nothing on the board but the FPGA? Providing for power measurement takes more than just lifting a diode and adding a series resistor unless the FPGA is the only thing on the board. Also, even if there is not a separate core rail, the I/Os have their own power pins even if used at 3.3 volts in this design. These days many designs use other voltages.
> As always, current consumption in an FPGA depends on the design it is > programmed with. But you know that.
That is what I want to measure, the combination of part and design. I have an ICE40 board and would be interested in doing comparisons with the XO2. They talk about the XO2 having low power in some modes, but I expect it is nothing like the ICE40. I'm about to do some power measurements on the ICE40 I have. The original devices from Silicon Blue were specified as something around 30 or 50 uA quiescent (can't remember off the top of my head). But they weren't really in production when Lattice took over and started dinking with the data sheet. They changed the quiescent from a max to a typ number and raised it to 100 uA for most in the family. I want to see *how* typical that number is and see just how much it goes up with a low power design. I get the impression the XO2 and XO3 may be competitive depending on that static/dynamic tradeoff. -- Rick
On 12/2/2014 4:20 AM, MK wrote:
> On 01/12/2014 14:30, Tim wrote: >> - non-volatile FPGA plus FTDI USB chip >> - connects to an Android host mode USB port >> - application software in Lua, with Java interface/driver >> - high-level Gideros software for whizzy graphics >> - FPGA firmware samples, including logic analyzer in source >> >> also works on a PC - useful for reprogramming the FPGA. >> >> Everything open source. >> >> www.bugblat.com/products/fan >> >> -- >> Tim > Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I > think I'll buy one. > I'm really pleased to see the open source, VHDL, LUA and Android host - > nice combination.
I think you sent me an email, although it may have been intended for the newsgroup. I tried to reply but the return address is bad and I can't seem to make it good. -- Rick
On 04/12/2014 01:56, rickman wrote:
> On 12/3/2014 6:25 PM, Tim wrote: >> On 03/12/2014 21:52, rickman wrote: >>> On 12/3/2014 11:39 AM, Tim wrote: >>>> On 02/12/2014 09:20, MK wrote: >>>>> On 01/12/2014 14:30, Tim wrote: >>>>>> - non-volatile FPGA plus FTDI USB chip >>>>>> - connects to an Android host mode USB port >>>>>> - application software in Lua, with Java interface/driver >>>>>> - high-level Gideros software for whizzy graphics >>>>>> - FPGA firmware samples, including logic analyzer in source >>>>>> >>>>>> also works on a PC - useful for reprogramming the FPGA. >>>>>> >>>>>> Everything open source. >>>>>> >>>>>> www.bugblat.com/products/fan >>>>>> >>>>>> -- >>>>>> Tim >>>>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA >>>>> but I >>>>> think I'll buy one. >>>>> I'm really pleased to see the open source, VHDL, LUA and Android >>>>> host - >>>>> nice combination. >>>>> >>>>> Michael Kellett >>>> >>>> The ICE40 non-volatile memory is OTP. You can also program the SRAM >>>> directly, but OTP is a problem in some applications. >>>> >>>> And this board is a spin-off from a bigger project, for which the >>>> XO2 is >>>> the best fit. >>> >>> Does the board have support for measuring power consumption of the XO2? >>> Different rails? >>> >> >> There's only one rail - 3.3V. This flavor of the XO2 has an internal >> regulator for the core voltage. >> >> You can measure current draw by one of >> - a USB current meter, easy to find on eBay >> - lift the Schottky in the power input and replace with a 0.1R resistor. > > There is nothing on the board but the FPGA? Providing for power > measurement takes more than just lifting a diode and adding a series > resistor unless the FPGA is the only thing on the board. Also, even if > there is not a separate core rail, the I/Os have their own power pins > even if used at 3.3 volts in this design. These days many designs use > other voltages. > > >> As always, current consumption in an FPGA depends on the design it is >> programmed with. But you know that. > > That is what I want to measure, the combination of part and design. I > have an ICE40 board and would be interested in doing comparisons with > the XO2. They talk about the XO2 having low power in some modes, but I > expect it is nothing like the ICE40. > > I'm about to do some power measurements on the ICE40 I have. The > original devices from Silicon Blue were specified as something around 30 > or 50 uA quiescent (can't remember off the top of my head). But they > weren't really in production when Lattice took over and started dinking > with the data sheet. They changed the quiescent from a max to a typ > number and raised it to 100 uA for most in the family. I want to see > *how* typical that number is and see just how much it goes up with a low > power design. I get the impression the XO2 and XO3 may be competitive > depending on that static/dynamic tradeoff. >
There isn't much on the board - you can download the schematic and check. Most of the components are various protection devices and they should not affect the result, particularly if you do a comparison against an unconfigured FPGA. That would also remove th effect of the FTDI device. A couple of config pins have pullups - not really needed because the chip is programmed via JTAG - but you should be able to calculate their current drain. -- Tim
On 05/12/2014 12:09, rickman wrote:
> On 12/2/2014 4:20 AM, MK wrote: >> On 01/12/2014 14:30, Tim wrote: >>> - non-volatile FPGA plus FTDI USB chip >>> - connects to an Android host mode USB port >>> - application software in Lua, with Java interface/driver >>> - high-level Gideros software for whizzy graphics >>> - FPGA firmware samples, including logic analyzer in source >>> >>> also works on a PC - useful for reprogramming the FPGA. >>> >>> Everything open source. >>> >>> www.bugblat.com/products/fan >>> >>> -- >>> Tim >> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I >> think I'll buy one. >> I'm really pleased to see the open source, VHDL, LUA and Android host - >> nice combination. > > I think you sent me an email, although it may have been intended for the > newsgroup. I tried to reply but the return address is bad and I can't > seem to make it good. >
Hello, I meant to post to the group but I'm forever clicking the wrong button in Thunderbird. Sorry. I'm trying to get a couple of new ICE40 designs up and running (used an 'HX1k before with no real trouble) and having problems with PLLs (trying to simulate and also working out which pins the ref input can use - Lattice say any GBIN but the ICECube tools says only two pins near the PLL power pins). I was wondering if anyone has actually used the PLLs. I'm also having no joy in getting slave spi mode to work (on 'HX4k) - once again this was OK on the 1K part but there are still a few things to try. Michael Kellett.
On 12/6/2014 9:56 AM, MK wrote:
> On 05/12/2014 12:09, rickman wrote: >> On 12/2/2014 4:20 AM, MK wrote: >>> On 01/12/2014 14:30, Tim wrote: >>>> - non-volatile FPGA plus FTDI USB chip >>>> - connects to an Android host mode USB port >>>> - application software in Lua, with Java interface/driver >>>> - high-level Gideros software for whizzy graphics >>>> - FPGA firmware samples, including logic analyzer in source >>>> >>>> also works on a PC - useful for reprogramming the FPGA. >>>> >>>> Everything open source. >>>> >>>> www.bugblat.com/products/fan >>>> >>>> -- >>>> Tim >>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I >>> think I'll buy one. >>> I'm really pleased to see the open source, VHDL, LUA and Android host - >>> nice combination. >> >> I think you sent me an email, although it may have been intended for the >> newsgroup. I tried to reply but the return address is bad and I can't >> seem to make it good. >> > Hello, I meant to post to the group but I'm forever clicking the wrong > button in Thunderbird. Sorry. > > I'm trying to get a couple of new ICE40 designs up and running (used an > 'HX1k before with no real trouble) and having problems with PLLs (trying > to simulate and also working out which pins the ref input can use - > Lattice say any GBIN but the ICECube tools says only two pins near the > PLL power pins). I was wondering if anyone has actually used the PLLs. > I'm also having no joy in getting slave spi mode to work (on 'HX4k) - > once again this was OK on the 1K part but there are still a few things > to try.
I feel your pain with regards to T-bird. I seldom make that mistake now but at first it was a struggle. Keep us informed with your progress using the ICE40 parts. Maybe start a new thread. I am on Lattice's distribution list for EOL's and such. I just got a notice that they are deleting one of the two packages for the ultra parts. They say they had *no* design wins in the 20 pin package. I'm not entirely surprised with only 12 I/Os. They can't seem to find a middle ground. The emphasis for FPGAs seems to be more on package size than low pin count really. They don't go with any easier to use packages (read larger or non-BGA) with lower pin counts, but rather small packages regardless of pin count. I guess handheld is driving the market these days. Space is at a premium while I/O counts still need to be generous. -- Rick