Hi I have no knowledge of PCIExpress protocol. The questions I have are: (1) where do I start to learn PCIE protocol ? (2) I am an experienced embedded systems programmer. How long would it take to implement PCIE stack in C/C++ ? (3) Any pointers to documentation of this protocol or examples would be useful thanks in advance Abdex --------------------------------------- Posted through http://www.EmbeddedRelated.com
PCIExpress stack
Started by ●June 5, 2015
Reply by ●June 7, 20152015-06-07
On Fri, 05 Jun 2015 07:04:57 -0500, "abradax" <106331@EmbeddedRelated> wrote:>Hi > >I have no knowledge of PCIExpress protocol. >The questions I have are: >(1) where do I start to learn PCIE protocol ? >(2) I am an experienced embedded systems programmer. How long would it >take to implement PCIE stack in C/C++ ? >(3) Any pointers to documentation of this protocol or examples would be >useful > >thanks in advance >PCIe doesn't have a "stack" like Ethernet or USB. The hardware uses the serial lanes to make the end device look like old PCI, which is itself a memory/IO bus without protocol. There is a lot of protocol, but it's done in hardware on both ends, for instance inside an x86 CPU, and in some hardcore logic in an FPGA or ASIC. You can program an FPGA to be a PCIe endpoint (assuming it has the hard IP) and it can become a memory-mapped region in the CPU address space. All your program has to do is map it from its physical space (assigned by the BIOS) into something a program can reach. We do that in Linux, with dev/mem or something, and there must be some way in Windows. PCIe is supposed to be fully transparent to PCI, so all that configuration space/BIOS/interrupt stuff is supposed to just work. It seems to. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●June 7, 20152015-06-07
On Sun, 07 Jun 2015 13:49:14 -0700, John Larkin <jlarkin@highlandtechnology.com> wrote:>On Fri, 05 Jun 2015 07:04:57 -0500, "abradax" <106331@EmbeddedRelated> >wrote: > >>Hi >> >>I have no knowledge of PCIExpress protocol. >>The questions I have are: >>(1) where do I start to learn PCIE protocol ? >>(2) I am an experienced embedded systems programmer. How long would it >>take to implement PCIE stack in C/C++ ? >>(3) Any pointers to documentation of this protocol or examples would be >>useful >> >>thanks in advance >> > >PCIe doesn't have a "stack" like Ethernet or USB. The hardware uses >the serial lanes to make the end device look like old PCI, which is >itself a memory/IO bus without protocol. There is a lot of protocol, >but it's done in hardware on both ends, for instance inside an x86 >CPU, and in some hardcore logic in an FPGA or ASIC. > >You can program an FPGA to be a PCIe endpoint (assuming it has the >hard IP) and it can become a memory-mapped region in the CPU address >space. All your program has to do is map it from its physical space >(assigned by the BIOS) into something a program can reach. We do that >in Linux, with dev/mem or something, and there must be some way in >Windows. > >PCIe is supposed to be fully transparent to PCI, so all that >configuration space/BIOS/interrupt stuff is supposed to just work. It >seems to.Well, you do need to set up the BARs, etc., for each device, and the mappings for most bridge chips, but in most cases that's not particularly hard.
Reply by ●June 7, 20152015-06-07
On Sun, 07 Jun 2015 16:02:10 -0500, Robert Wessel <robertwessel2@yahoo.com> wrote:>On Sun, 07 Jun 2015 13:49:14 -0700, John Larkin ><jlarkin@highlandtechnology.com> wrote: > >>On Fri, 05 Jun 2015 07:04:57 -0500, "abradax" <106331@EmbeddedRelated> >>wrote: >> >>>Hi >>> >>>I have no knowledge of PCIExpress protocol. >>>The questions I have are: >>>(1) where do I start to learn PCIE protocol ? >>>(2) I am an experienced embedded systems programmer. How long would it >>>take to implement PCIE stack in C/C++ ? >>>(3) Any pointers to documentation of this protocol or examples would be >>>useful >>> >>>thanks in advance >>> >> >>PCIe doesn't have a "stack" like Ethernet or USB. The hardware uses >>the serial lanes to make the end device look like old PCI, which is >>itself a memory/IO bus without protocol. There is a lot of protocol, >>but it's done in hardware on both ends, for instance inside an x86 >>CPU, and in some hardcore logic in an FPGA or ASIC. >> >>You can program an FPGA to be a PCIe endpoint (assuming it has the >>hard IP) and it can become a memory-mapped region in the CPU address >>space. All your program has to do is map it from its physical space >>(assigned by the BIOS) into something a program can reach. We do that >>in Linux, with dev/mem or something, and there must be some way in >>Windows. >> >>PCIe is supposed to be fully transparent to PCI, so all that >>configuration space/BIOS/interrupt stuff is supposed to just work. It >>seems to. > > >Well, you do need to set up the BARs, etc., for each device, and the >mappings for most bridge chips, but in most cases that's not >particularly hard.The BIOS generally does all that at boot time, just like PCI. Whatever OS you use, you can call whatever resources it has to find out where the configuration process put things. Or, bare metal, you can prowl config space yourself. On the device end, you do have to set up the BAR config registers, so that the BIOS knows what resources you need. In an FPGA, you've got to do that on purpose. If you are plugging in a commercial board or using a standard peripherial chip, that's usually all done for you. I guess an extreme do-it-yourself embedded system might not even have a BIOS, but then you could leap on the golden opportunity to NOT use PCIe. CPUs used to have memory busses that you could hang things on. Some still do. But many now only get out over the DRAM and USB and PCIe paths, which sort of suck for real embedded design. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
