"Theo Markettos" <theom+news@chiark.greenend.org.uk> wrote in message news:szd*2MTBv@news.chiark.greenend.org.uk...> glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >> Theo Markettos <theom+news@chiark.greenend.org.uk> wrote:...>> > Any time you move the PC into another register, for instance the >> > link >> > register R14, what you actually get is the address of the current >> > instruction plus 8. The reason for this dates back to the ARM1, >> > which had a >> > 3 stage pipeline, fetch-decode-execute. When you executed the >> > move, the >> > instruction fetch stage was already two instructions further on....>> > A bit like the branch delay slot on MIPS, exposure of this >> > microarchitectural artifact to the ISA has meant that all 32 bit >> > ARMs use >> > this current+8, even though they don't have 3 stage pipelines any >> > more. >> >> Is there a compensating branch instruction? > > AFAIR, it's 'MOV rN, pc' that's affected.Yes, and AIUI that can be a benefit. It allows the program to use various types of branch instruction while still setting the return address properly. For example, mov r14, pc bx somewhere or mov r14, pc ldr pc, =target In each case R14 will hold the address *after* the branch, not the address of the branch. When I first saw that I thought it was weird. It still looks odd to someone like me who is used to PC pointing to the next instruction. James
Could you explain ARM Branch with Link (BL) instruction considering prefetch?
Started by ●July 30, 2015
Reply by ●September 6, 20152015-09-06
