Forums

8051 memory interfacing questions

Started by andrew queisser February 3, 2004
I'm trying to understand what my options are when
it comes to interfacing memory to 8051. Am I correct
that:

- interfacing DRAM is complex (for a beginner)
- interfacing SRAM is more straightforward and is
really the only practical memory type for fast, random
access at the byte level (e.g. stack, heap)
- interfacing FlashRAM is also straightforward but
writing is more complex than just moving a byte
to an address
- various forms of serial memory use lowest count
of I/O pins but are really,really slow.

So, as a novice, do I have any options other than
SRAM if I want a large external heap and stack?

Also, how does the SRAM access time spec relate
to the 8051 timing on port 0 and 2? In one machine
cycle P0 puts out low addr and then reads/writes
data. Does that mean I need to use SRAM with
an access time of less than 1/6 of a machine cycle?

Thanks,
Andrew


"andrew queisser" <andrew.queisser@hp.com> wrote in
news:401fd848$1@usenet01.boi.hp.com: 

> I'm trying to understand what my options are when > it comes to interfacing memory to 8051. Am I correct > that: > > - interfacing DRAM is complex (for a beginner)
And the 8051 cannot directly interface to traditional row/column DRAM without extra hardware.
> - interfacing SRAM is more straightforward and is > really the only practical memory type for fast, random > access at the byte level (e.g. stack, heap)
Extremely simple, add an 8-bit latch and you're done.
> - interfacing FlashRAM is also straightforward but > writing is more complex than just moving a byte > to an address
Correct. You cannot have a C compiler treat flash like regular RAM but you can put const vars and functions there.
> - various forms of serial memory use lowest count > of I/O pins but are really,really slow.
They should be thought of more like storage than memory (e.g. more like a disk drive than memory).
> So, as a novice, do I have any options other than > SRAM if I want a large external heap and stack?
FRAM (www.ramtron.com) but what's wrong with SRAM?
> Also, how does the SRAM access time spec relate > to the 8051 timing on port 0 and 2? In one machine > cycle P0 puts out low addr and then reads/writes > data. Does that mean I need to use SRAM with > an access time of less than 1/6 of a machine cycle?
Pretty much any SRAM today can keep up with a traditional 8051 bus cycle time. Faster 8051s have wait-state insertion capabilities. -- - Mark -> --
andrew queisser wrote:

> I'm trying to understand what my options are when > it comes to interfacing memory to 8051. Am I correct > that: > > - interfacing DRAM is complex (for a beginner)
Yes - with the address capabilities of a 8051 (limited to 64 kbytes) there is no sense to take the trouble.
> - interfacing SRAM is more straightforward and is > really the only practical memory type for fast, random > access at the byte level (e.g. stack, heap)
Yes. For stack, see later.
> - interfacing FlashRAM is also straightforward but > writing is more complex than just moving a byte > to an address
Flash is not RAM - the write procedure is complex and it cannot be used as general-purpose writable storage.
> - various forms of serial memory use lowest count > of I/O pins but are really,really slow.
Yes
> So, as a novice, do I have any options other than > SRAM if I want a large external heap and stack?
Not much. Please note that the hardware stack must be in on-chip RAM for the 8051 family devices. There are no non-clumsy ways to have large memory with an 8051 - if the memory requirement exceeds 64 kilobytes, consider a larger processor, e.g. an Atmel AT91 ARM, the address arithmetic gets difficult with an eight-bit arithmetic unit.
> Also, how does the SRAM access time spec relate > to the 8051 timing on port 0 and 2? In one machine > cycle P0 puts out low addr and then reads/writes > data. Does that mean I need to use SRAM with > an access time of less than 1/6 of a machine cycle?
Most versions of 8051 are far slower than current static RAMs - it should not be a problem. HTH Tauno Voipio tauno voipio @ iki fi
In article <_vRTb.563$sT2.444@read3.inet.fi>, Tauno Voipio <tauno.voipio
@iki.fi.NOSPAM.invalid> writes
>andrew queisser wrote: > >> I'm trying to understand what my options are when >> it comes to interfacing memory to 8051. Am I correct >> that: >> >> - interfacing DRAM is complex (for a beginner) > >Yes - with the address capabilities of a 8051 (limited to >64 kbytes) there is no sense to take the trouble.
However 8051's can bank switch to a lot more. But then again the Analoge Devices, Dallas and Phillips parts can address up to 8Megan byte code and 8Megabyte data space.... The Philips Mx range have 192Kb on chip flash But that was not the question,... The 8051 does not drive DRAM. If you want EXTERNAL DRAM you will have to do your own refresh ccts.
>> - interfacing SRAM is more straightforward and is >> really the only practical memory type for fast, random >> access at the byte level (e.g. stack, heap)
Yes. Very simple
> >Yes. For stack, see later.
Yes, but not for stack. the stack is internal to the chip if you need it.
>> - interfacing FlashRAM is also straightforward but >> writing is more complex than just moving a byte >> to an address > >Flash is not RAM - the write procedure is complex and >it cannot be used as general-purpose writable storage.
The right procedure is not complex but you would not use FLASH in place of RAM. It tends to replace EEPROM, ROM, EPROM and ROM. Though it is useful for data that has to be backed up of retained after powoer down. EG in smart cards and phone sims.
>> - various forms of serial memory use lowest count >> of I/O pins but are really,really slow. >Yes >> So, as a novice, do I have any options other than >> SRAM if I want a large external heap and stack? > >Not much. Please note that the hardware stack must >be in on-chip RAM for the 8051 family devices.
However in a good compiler the need for a stack is greatly reduced. Also a good compiler will do data overlaying and reduce the amount of RAM needed drastically. I have seen a projected 115 bytes of data only tack up 20 bytes in the compiled program.
>There are no non-clumsy ways to have large memory >with an 8051 - if the memory requirement exceeds >64 kilobytes, consider a larger processor, e.g. >an Atmel AT91 ARM, the address arithmetic gets >difficult with an eight-bit arithmetic unit.
This is incorrect. The Philips MX parts go to 192 on chip the Analoge Devices and Dallas parts can go up to 16MB, they have 24 bit addressing.
>> Also, how does the SRAM access time spec relate >> to the 8051 timing on port 0 and 2? In one machine >> cycle P0 puts out low addr and then reads/writes >> data. Does that mean I need to use SRAM with >> an access time of less than 1/6 of a machine cycle? > >Most versions of 8051 are far slower than current >static RAMs - it should not be a problem.
Some are single cycle but have an effective speed of about 100Mhz the Atmel 51's will go to 66Mhz but there should be no problem with RAM. The RAM will be faster than the FLASH on them anyway. /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/\ /\/\/ chris@phaedsys.org www.phaedsys.org \/\/ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/
"andrew queisser" <andrew.queisser@hp.com> wrote in news:401fd848$1
@usenet01.boi.hp.com:
> So, as a novice, do I have any options other than > SRAM if I want a large external heap and stack? >
Unless there is a variant that does otherwise, the 8051 stack must be in internal memory, you have no choice on that. -- Richard
Chris Hills wrote:
> >>There are no non-clumsy ways to have large memory >>with an 8051 - if the memory requirement exceeds >>64 kilobytes, consider a larger processor, e.g. >>an Atmel AT91 ARM, the address arithmetic gets >>difficult with an eight-bit arithmetic unit. > > > This is incorrect. The Philips MX parts go to 192 on chip the Analoge > Devices and Dallas parts can go up to 16MB, they have 24 bit addressing. >
Chris, please: Bank-switching *is* clumsy. In the 8051 architecture there is no *simple* way to address beyond 64 kbytes. Tauno Voipio tauno voipio @ iki fi
In article <2BTTb.644$sT2.582@read3.inet.fi>, Tauno Voipio <tauno.voipio
@iki.fi.NOSPAM.invalid> writes
>Chris Hills wrote: >> >>>There are no non-clumsy ways to have large memory >>>with an 8051 - if the memory requirement exceeds >>>64 kilobytes, consider a larger processor, e.g. >>>an Atmel AT91 ARM, the address arithmetic gets >>>difficult with an eight-bit arithmetic unit. >> >> >> This is incorrect. The Philips MX parts go to 192 on chip the Analoge >> Devices and Dallas parts can go up to 16MB, they have 24 bit addressing. >> > >Chris, please: Bank-switching *is* clumsy. In the 8051 >architecture there is no *simple* way to address beyond >64 kbytes.
I have a Philips part with 192K of on chip Flash and linear addressing ie no bank switching. However I agree that banking is clumsy and if you do need to do a lot of banking may be you have the wrong chip though I know people who are putting compact Flash cards on to 8051's with file systems. There are times when you only need a small MCU but a lot of storage. Regards Chris. /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/\ /\/\/ chris@phaedsys.org www.phaedsys.org \/\/ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/
>> This is incorrect. The Philips MX parts go to 192 on chip the Analoge >> Devices and Dallas parts can go up to 16MB, they have 24 bit addressing. >> > >Chris, please: Bank-switching *is* clumsy. In the 8051 >architecture there is no *simple* way to address beyond >64 kbytes.
You probably should read the datasheet of the Dallas parts then first. There you set a register in the sfr and then there is NO bankswitching needed. Flat 16MB address space! Markus
Chris Hills wrote:

> However 8051's can bank switch to a lot more. But then again the > Analoge Devices, Dallas and Phillips parts can address up to 8Megan byte > code and 8Megabyte data space.... > > The Philips Mx range have 192Kb on chip flash
I can find P89C669 with 96KF, and MX core, but the 192KF model eludes me.... part number ? -jg
In article <VsXTb.20622$ws.2742756@news02.tsnz.net>, Jim Granville
<no.spam@designtools.co.nz> writes
>Chris Hills wrote: > >> However 8051's can bank switch to a lot more. But then again the >> Analoge Devices, Dallas and Phillips parts can address up to 8Megan byte >> code and 8Megabyte data space.... >> >> The Philips Mx range have 192Kb on chip flash > > I can find P89C669 with 96KF, and MX core, but the 192KF >model eludes me.... part number ?
It is the 89C51MC2 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/\ /\/\/ chris@phaedsys.org www.phaedsys.org \/\/ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/