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What is the Best PCB Layout software ? (Money no object)

Started by Anton Erasmus January 12, 2004
Hi,

There have been quite a few discussion regarding cheap PCB/Schematic
layout packages recently. What package(s) are considered the best if
money is no object ? What features does this/these package(s) have
that are not available in the cheaper PCB/Schematic packages ?

What packages are used to do the layout of these new generation ultra
compact cell phones and other high volume consumer products ?

Regards
   Anton Erasmus

"Anton Erasmus" <junk@junk.net> schreef in bericht
news:nr16009pb1bvm2r0sa9hvlb08qlm8t4mts@4ax.com...
> Hi, > > There have been quite a few discussion regarding cheap PCB/Schematic > layout packages recently. What package(s) are considered the best if > money is no object ? What features does this/these package(s) have > that are not available in the cheaper PCB/Schematic packages ? > > What packages are used to do the layout of these new generation ultra > compact cell phones and other high volume consumer products ? > > Regards > Anton Erasmus >
I have experienced very expensive en powerfull packages like ORCAD en ULTIBOARD. But eagle is a cheap one (http://www.cadsoft.de/prices.htm) and can make wonders.
I don't know about phones but I know people like Wind River use PowerPCB &
Blaze Router from Mentor.

I suspect the major difference would be rules base routing. i.e. it's
possible to say these 2 traces have to run next to each other, have to have
a certain clearance, have to have a certain time delay, have to have a
certain impedance. etc

Also more than 4 layer routing, split or mixed plane, and other things like
design for test and design for manufacturing.

Spectra is also a very big name in autorouting.

A decent spec on these systems is generally in the tens of thousands of
dollars.

"Anton Erasmus" <junk@junk.net> wrote in message
news:nr16009pb1bvm2r0sa9hvlb08qlm8t4mts@4ax.com...
> Hi, > > There have been quite a few discussion regarding cheap PCB/Schematic > layout packages recently. What package(s) are considered the best if > money is no object ? What features does this/these package(s) have > that are not available in the cheaper PCB/Schematic packages ? > > What packages are used to do the layout of these new generation ultra > compact cell phones and other high volume consumer products ? > > Regards > Anton Erasmus >
vinger wrote:
> > "Anton Erasmus" <junk@junk.net> schreef in bericht > news:nr16009pb1bvm2r0sa9hvlb08qlm8t4mts@4ax.com... > > Hi, > > > > There have been quite a few discussion regarding cheap PCB/Schematic > > layout packages recently. What package(s) are considered the best if > > money is no object ? What features does this/these package(s) have > > that are not available in the cheaper PCB/Schematic packages ? > > > > What packages are used to do the layout of these new generation ultra > > compact cell phones and other high volume consumer products ? > > > > Regards > > Anton Erasmus > > > > I have experienced very expensive en powerfull packages like ORCAD en > ULTIBOARD. > But eagle is a cheap one (http://www.cadsoft.de/prices.htm) and can make > wonders.
One thing it can't do (without screwing up the DRC) is holes in a PAD. I am using a small regulator that requires heat spreaders on the top and bottom of the board connected by vias directly under the thermal pad on the bottom of the package. I know this is not normal, but TI recommends it. I was never able to get rid of the DRC errors this produced.
"Ralph Malph" <noone@yahoo.com> wrote in message
news:40036859.F8EA05E7@yahoo.com...

> One thing it can't do (without screwing up the DRC) is holes in a PAD. > I am using a small regulator that requires heat spreaders on the top and > bottom of the board connected by vias directly under the thermal pad on > the bottom of the package. I know this is not normal, but TI recommends > it. I was never able to get rid of the DRC errors this produced.
If this is the package I remember, you can make the thermal pad a small pad with THERMAL=OFF inside a rectangle on the top layer. A pain, but no DRC complaints.
Ian McBride wrote:
> > "Ralph Malph" <noone@yahoo.com> wrote in message > news:40036859.F8EA05E7@yahoo.com... > > > One thing it can't do (without screwing up the DRC) is holes in a PAD. > > I am using a small regulator that requires heat spreaders on the top and > > bottom of the board connected by vias directly under the thermal pad on > > the bottom of the package. I know this is not normal, but TI recommends > > it. I was never able to get rid of the DRC errors this produced. > > If this is the package I remember, you can make the thermal pad a small pad > with THERMAL=OFF inside a rectangle on the top layer. A pain, but no DRC > complaints.
I am not trying to make a thermal. I am trying to make a fairly large rectangular pad with six holes (vias) in it. The entire rectangle needs to have the solder mask removed from it. I guess I could have split the pad up into six equal, rectangular areas as pads. But they should be touching and I don't think I can get this past the DRC either unless I allow everything to touch. I believe I have object spacing set for 10 mil at the moment. Or could I use a polygon to open up an area in the solder mask? I did not try much in that area.
Ralph Malph wrote:
> > Ian McBride wrote: > > > > "Ralph Malph" <noone@yahoo.com> wrote in message > > news:40036859.F8EA05E7@yahoo.com... > > > > > One thing it can't do (without screwing up the DRC) is holes in a PAD. > > > I am using a small regulator that requires heat spreaders on the top and > > > bottom of the board connected by vias directly under the thermal pad on > > > the bottom of the package. I know this is not normal, but TI recommends > > > it. I was never able to get rid of the DRC errors this produced. > > > > If this is the package I remember, you can make the thermal pad a small pad > > with THERMAL=OFF inside a rectangle on the top layer. A pain, but no DRC > > complaints. > > I am not trying to make a thermal. I am trying to make a fairly large > rectangular pad with six holes (vias) in it. The entire rectangle needs > to have the solder mask removed from it. I guess I could have split the > pad up into six equal, rectangular areas as pads. But they should be > touching and I don't think I can get this past the DRC either unless I > allow everything to touch. I believe I have object spacing set for 10 > mil at the moment. > > Or could I use a polygon to open up an area in the solder mask? I did > not try much in that area.
By George! That did it! I can draw a rectangle on the tStop layer to open up some copper around the six pads. I already found somewhere that you can put the same name on multiple pads by adding a $ or # or something similar to the name. So I could use six pads inside a solder mask rectangle to add these to the part. However, there are still four more vias that are outside this pad area that need a surface plane which is under solder mask. I believe adding a rectangle to the copper layer of a part causes problems because it does not have the signal name. Or maybe a rectangle does not need a name? But will that cause other problems such as a copper pour leaving a gap around it? The part according to TI should be like this... +---------------------+ | +-----------+ | | O | o o o | O | | | | | | | | | | O | o o o | O | | +-----------+ | +---------------------+ The inner rectangle has no solder mask and six 0.013" vias. The outer rectangle has solder mask and 0.018" vias. I don't see how to do the outer ones.
Ralph Malph schrieb:

> > Or could I use a polygon to open up an area in the solder mask? I did > > not try much in that area. > > By George! That did it! I can draw a rectangle on the tStop layer to > open up some copper around the six pads. I already found somewhere that > you can put the same name on multiple pads by adding a $ or # or > something similar to the name. So I could use six pads inside a solder > mask rectangle to add these to the part. > ... > The inner rectangle has no solder mask and six 0.013" vias. The outer > rectangle has solder mask and 0.018" vias. I don't see how to do the > outer ones.
Sorry, I really can't see your problem here. EAGLE does not support extended pad shapes in packages without DRC complaints, but you can draw about anything directly in your board (most often using polygons makes sense) with perfect match of specifications and DRC. However, you can include non-copper objects (like stop mask) in the package definition. I have written about this several times in eagle.support.eng, I thought you had noticed that. -- Dipl.-Ing. Tilmann Reh Autometer GmbH Siegen - Elektronik nach Ma&#2013265951;. http://www.autometer.de ================================================================== In a world without walls and fences, who needs Windows and Gates ? (Sun Microsystems)
Ralph,

try to use polygones. Don't forget to give it/them the right signal name. If
the signal name (e.g. GND) is the same for different polygones or Vias,
Eagle will connect them together ( or tries it). I hope it helps you....

...kay

"Ralph Malph" <noone@yahoo.com> schrieb im Newsbeitrag
news:40037BCE.9A6DFF99@yahoo.com...
> Ralph Malph wrote: > > > > Ian McBride wrote: > > > > > > "Ralph Malph" <noone@yahoo.com> wrote in message > > > news:40036859.F8EA05E7@yahoo.com... > > > > > > > One thing it can't do (without screwing up the DRC) is holes in a
PAD.
> > > > I am using a small regulator that requires heat spreaders on the top
and
> > > > bottom of the board connected by vias directly under the thermal pad
on
> > > > the bottom of the package. I know this is not normal, but TI
recommends
> > > > it. I was never able to get rid of the DRC errors this produced. > > > > > > If this is the package I remember, you can make the thermal pad a
small pad
> > > with THERMAL=OFF inside a rectangle on the top layer. A pain, but no
DRC
> > > complaints. > > > > I am not trying to make a thermal. I am trying to make a fairly large > > rectangular pad with six holes (vias) in it. The entire rectangle needs > > to have the solder mask removed from it. I guess I could have split the > > pad up into six equal, rectangular areas as pads. But they should be > > touching and I don't think I can get this past the DRC either unless I > > allow everything to touch. I believe I have object spacing set for 10 > > mil at the moment. > > > > Or could I use a polygon to open up an area in the solder mask? I did > > not try much in that area. > > By George! That did it! I can draw a rectangle on the tStop layer to > open up some copper around the six pads. I already found somewhere that > you can put the same name on multiple pads by adding a $ or # or > something similar to the name. So I could use six pads inside a solder > mask rectangle to add these to the part. > > However, there are still four more vias that are outside this pad area > that need a surface plane which is under solder mask. I believe adding > a rectangle to the copper layer of a part causes problems because it > does not have the signal name. Or maybe a rectangle does not need a > name? But will that cause other problems such as a copper pour leaving > a gap around it? > > The part according to TI should be like this... > > +---------------------+ > | +-----------+ | > | O | o o o | O | > | | | | > | | | | > | O | o o o | O | > | +-----------+ | > +---------------------+ > > The inner rectangle has no solder mask and six 0.013" vias. The outer > rectangle has solder mask and 0.018" vias. I don't see how to do the > outer ones.
Anton Erasmus <junk@junk.net> wrote in message news:<nr16009pb1bvm2r0sa9hvlb08qlm8t4mts@4ax.com>...
> Hi, > > There have been quite a few discussion regarding cheap PCB/Schematic > layout packages recently. What package(s) are considered the best if > money is no object ? What features does this/these package(s) have > that are not available in the cheaper PCB/Schematic packages ? > > What packages are used to do the layout of these new generation ultra > compact cell phones and other high volume consumer products ? > > Regards > Anton Erasmus
I think it is up to what does start with? I'm used PowerPCB. :)