Soldering Thermal Pads

I'm helping with a board design of a few surface mount components with large thermal loads.  The main problem is a part that has large pads.  The guy is laying it out ignoring the suggestions of the data sheet and simply put five 16 mil drill vias to the bottom layer with a lot of copper.  That's about like connecting with five thermal breaks, 50 mil wide and 62 mil long.  

He wants to put them in the pad tenting them on the bottom to minimize wicking.  I've never heard of that.  Is that a thing?  I've always heard that vias simply should not be in the pad, rather ring the pad with lots of copper.  Then you can get a significant number of them, adequate to connect the bottom layer to the top thermally.  

How do you do  it? 

-- 

Rick C.

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On 2020-12-16 Rick C wrote in comp.arch.embedded:
> I'm helping with a board design of a few surface mount components with large thermal loads.  The main problem is a part that has large pads.  The guy is laying it out ignoring the suggestions of the data sheet and simply put five 16 mil drill vias to the bottom layer with a lot of copper.  That's about like connecting with five thermal breaks, 50 mil wide and 62 mil long.  
>
> He wants to put them in the pad tenting them on the bottom to minimize wicking.  I've never heard of that.  Is that a thing?  I've always heard that vias simply should not be in the pad, rather ring the pad with lots of copper.  Then you can get a significant number of them, adequate to connect the bottom layer to the top thermally.  
>
> How do you do  it? 

That depends on the datasheet recommendations and/or our own judgement. But
we do use vias in pads for better thermal connection to a plane if that is
required. I don't know what you mean by 'tenting', but we do use soldermask
over those vias (and all others) on the back of the board. Is that what you
mean? Never had problems with this. Another option is via plugging, but
thats extra board cost and I have no experience with it.


-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

One Bell System - it works.

Rick C <gnuarm.deletethisbit@gmail.com> wrote:
> He wants to put them in the pad tenting them on the bottom to minimize
> wicking.  I've never heard of that.  Is that a thing?  I've always heard
> that vias simply should not be in the pad, rather ring the pad with lots
> of copper.  Then you can get a significant number of them, adequate to
> connect the bottom layer to the top thermally.
> 
> How do you do  it? 

It really depends on the assembly process:

Hand pasting and oven reflow: vias + untented on the bottom; wicking helps
excess paste to wick through and stop the IC floating on a
puddle of solder on its thermal pad.

Automated assembly: ask your assembly house as to what has the best yield
If they don't know, follow the manufacturer's instructions.


I understand that some IC vendors recommend a grid pattern of paste (not
just a single aperture) to aid paste control and prevent over-application
when doing it by hand.  These can be more difficult to apply if you don't
have a proper stencil.

Really it's something your CAD tool should handle with the right holes,
copper and soldermask apertures for the specific package, according to the
manufacturer's instructions.  Some of the more basic tools and their
libraries don't seem very good at it though.

Theo

On Wednesday, December 16, 2020 at 6:50:06 PM UTC-5, Stef wrote:
> On 2020-12-16 Rick C wrote in comp.arch.embedded: 
> > I'm helping with a board design of a few surface mount components with large thermal loads. The main problem is a part that has large pads. The guy is laying it out ignoring the suggestions of the data sheet and simply put five 16 mil drill vias to the bottom layer with a lot of copper. That's about like connecting with five thermal breaks, 50 mil wide and 62 mil long. 
> > 
> > He wants to put them in the pad tenting them on the bottom to minimize wicking. I've never heard of that. Is that a thing? I've always heard that vias simply should not be in the pad, rather ring the pad with lots of copper. Then you can get a significant number of them, adequate to connect the bottom layer to the top thermally. 
> > 
> > How do you do it?
> That depends on the datasheet recommendations and/or our own judgement. But 
> we do use vias in pads for better thermal connection to a plane if that is 
> required. I don't know what you mean by 'tenting', but we do use soldermask 
> over those vias (and all others) on the back of the board. Is that what you 
> mean? Never had problems with this. Another option is via plugging, but 
> thats extra board cost and I have no experience with it. 

I've always had a hard time getting PCB fab houses to not clip my silkscreen around vias and pads.  The problem is they use much larger clipping regions than would seem to be required.  The assembly house was the middle man, but kept talking about how bad tented vias are, referring to closing off the via opening by the silkscreen or solder mask, potentially causing damage to the boards somehow.  They seemed to think it could cause bubbles in the solder mask or something.  I did get them to clip a lot smaller but they still clipped.  

If you tent the back side and cover the front side with solder paste and a chip, where does the air go that is trapped in the via when the board is reflowed raising the temperature so much?  At 250°C the pressure in the via is going to rise to 2 atm.  I expect if it doesn't do anything to the board it would tend to push the chip up and burp.  But then it depends on the number of size of the vias.  Lots of smaller vias have less volume than fewer large ones. 

The chip data sheet does not show any vias under the pads.  They show large areas of copper radiating from the chip.   VNH5019A

Any idea how much plating is found on vias on a board with the typical 1 oz copper?  I assume that start with 1/2 oz and plate up to 1 oz, so adding 1/2 oz.  Does that equate to 1/2 oz copper in the vias or somewhat less due to diffusion limitations? 

-- 

Rick C.

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On Wednesday, December 16, 2020 at 10:13:31 PM UTC-5, Rick C wrote:
> On Wednesday, December 16, 2020 at 6:50:06 PM UTC-5, Stef wrote: 
> > On 2020-12-16 Rick C wrote in comp.arch.embedded: 
> > > I'm helping with a board design of a few surface mount components with large thermal loads. The main problem is a part that has large pads. The guy is laying it out ignoring the suggestions of the data sheet and simply put five 16 mil drill vias to the bottom layer with a lot of copper. That's about like connecting with five thermal breaks, 50 mil wide and 62 mil long. 
> > > 
> > > He wants to put them in the pad tenting them on the bottom to minimize wicking. I've never heard of that. Is that a thing? I've always heard that vias simply should not be in the pad, rather ring the pad with lots of copper. Then you can get a significant number of them, adequate to connect the bottom layer to the top thermally. 
> > > 
> > > How do you do it? 
> > That depends on the datasheet recommendations and/or our own judgement. But 
> > we do use vias in pads for better thermal connection to a plane if that is 
> > required. I don't know what you mean by 'tenting', but we do use soldermask 
> > over those vias (and all others) on the back of the board. Is that what you 
> > mean? Never had problems with this. Another option is via plugging, but 
> > thats extra board cost and I have no experience with it.
> I've always had a hard time getting PCB fab houses to not clip my silkscreen around vias and pads. The problem is they use much larger clipping regions than would seem to be required. The assembly house was the middle man, but kept talking about how bad tented vias are, referring to closing off the via opening by the silkscreen or solder mask, potentially causing damage to the boards somehow. They seemed to think it could cause bubbles in the solder mask or something. I did get them to clip a lot smaller but they still clipped. 
> 
> If you tent the back side and cover the front side with solder paste and a chip, where does the air go that is trapped in the via when the board is reflowed raising the temperature so much? At 250°C the pressure in the via is going to rise to 2 atm. I expect if it doesn't do anything to the board it would tend to push the chip up and burp. But then it depends on the number of size of the vias. Lots of smaller vias have less volume than fewer large ones. 
> 
> The chip data sheet does not show any vias under the pads. They show large areas of copper radiating from the chip. VNH5019A 
> 
> Any idea how much plating is found on vias on a board with the typical 1 oz copper? I assume that start with 1/2 oz and plate up to 1 oz, so adding 1/2 oz. Does that equate to 1/2 oz copper in the vias or somewhat less due to diffusion limitations? 

I found this.  https://www.ti.com/lit/an/snva419c/snva419c.pdf 

Page 6, 3.2 Rule2 : Thermal VIAS
A typical 12 mil diameter thru hole via with 0.5 oz copper side walls has a thermal resistance of 261°C /Watt.

So a 16 mil via would have about 200°C / watt.  Five of them is still 40°C / watt.  This design is going to need a lot more vias or more copper on the same side of the board. 

-- 

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209 

On 2020-12-16 Theo wrote in comp.arch.embedded:
>
> I understand that some IC vendors recommend a grid pattern of paste (not
> just a single aperture) to aid paste control and prevent over-application
> when doing it by hand.  These can be more difficult to apply if you don't
> have a proper stencil.

For larger (under chip) pads we always use a grid pattern. If I understood
correctly, the recommendation is to aim for 50-75% paste coverage on those
pads. But that ofcourse also depends on your stencil thickness.

The grid pattern also helps gasses from the solder paste escape and can
reduce voiding.

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Sanity is the trademark of a weak mind.
		-- Mark Harrold

On 2020-12-17 Rick C wrote in comp.arch.embedded:
> On Wednesday, December 16, 2020 at 6:50:06 PM UTC-5, Stef wrote:
>> On 2020-12-16 Rick C wrote in comp.arch.embedded: 
>> > I'm helping with a board design of a few surface mount components with large thermal loads. The main problem is a part that has large pads. The guy is laying it out ignoring the suggestions of the data sheet and simply put five 16 mil drill vias to the bottom layer with a lot of copper. That's about like connecting with five thermal breaks, 50 mil wide and 62 mil long. 
>> > 
>> > He wants to put them in the pad tenting them on the bottom to minimize wicking. I've never heard of that. Is that a thing? I've always heard that vias simply should not be in the pad, rather ring the pad with lots of copper. Then you can get a significant number of them, adequate to connect the bottom layer to the top thermally. 
>> > 
>> > How do you do it?
>> That depends on the datasheet recommendations and/or our own judgement. But 
>> we do use vias in pads for better thermal connection to a plane if that is 
>> required. I don't know what you mean by 'tenting', but we do use soldermask 
>> over those vias (and all others) on the back of the board. Is that what you 
>> mean? Never had problems with this. Another option is via plugging, but 
>> thats extra board cost and I have no experience with it. 
>
> I've always had a hard time getting PCB fab houses to not clip my silkscreen around vias and pads.  The problem is they use much larger clipping regions than would seem to be required.  The assembly house was the middle man, but kept talking about how bad tented vias are, referring to closing off the via opening by the silkscreen or solder mask, potentially causing damage to the boards somehow.  They seemed to think it could cause bubbles in the solder mask or something.  I did get them to clip a lot smaller but they still clipped.  
>

Weird, never had that problem. Yes, they clip soldermask and silkscreen around
pads, but never around vias. Silkscreen over a via is usually a bit distorted,
but if you have no other space to put it, it's better than nothing. Our pcb
package has an option to use soldermask over vias or not. We always put
soldermask over the vias and if that is in the gerbers, that is wat we get on
the boards. Never tried what happens of we don't put soldermaks over the vias
but do have silkscreen over them.

> If you tent the back side and cover the front side with solder paste and a chip, where does the air go that is trapped in the via when the board is reflowed raising the temperature so much?  At 250°C the pressure in the via is going to rise to 2 atm.  I expect if it doesn't do anything to the board it would tend to push the chip up and burp.  But then it depends on the number of size of the vias.  Lots of smaller vias have less volume than fewer large ones. 

The contribution of gasses from the solder paste itself is probably much
larger than that of the little bit of air in the vias. A paste grid
pattern can help to reduce problems with these gasses (voiding).
A page about that topic: https://fctsolder.com/solder-voiding/ 

> The chip data sheet does not show any vias under the pads.  They show large areas of copper radiating from the chip.   VNH5019A

The datasheet only shows some tested layouts and the thermal results. I
see no other recommendation than a "suggested pad layout". With these
pads and a little copper area on the side, you could place all the thermal
vias in the areas next to the pads and/or place them inside the pads. I
don't know what I would do in this case. Would also depend on the rest of
the layout. But I would use as much copper as possible on the top and then
decide where and how many thermal vias to use. A bit more compicated in
this case as the thermal pads are not in the same net. so you cannot just
connect all to a bottom ground plane.

> Any idea how much plating is found on vias on a board with the typical 1 oz copper?  I assume that start with 1/2 oz and plate up to 1 oz, so adding 1/2 oz.  Does that equate to 1/2 oz copper in the vias or somewhat less due to diffusion limitations? 

I'm not so much in the oz thing. What I always hear is that the finished
hole size of a plated hole is 0.1mm smaller than the drill. So when I 
design in a 0.3mm via, they use a 0.4mm drill and the expected plating
thickness inside the hole is 0.05mm.


-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Mr. Cole's Axiom:
	The sum of the intelligence on the planet is a constant; the
	population is growing.

On 17/12/2020 04:13, Rick C wrote:
> On Wednesday, December 16, 2020 at 6:50:06 PM UTC-5, Stef wrote:
>> On 2020-12-16 Rick C wrote in comp.arch.embedded:
>>> I'm helping with a board design of a few surface mount components
>>> with large thermal loads. The main problem is a part that has
>>> large pads. The guy is laying it out ignoring the suggestions of
>>> the data sheet and simply put five 16 mil drill vias to the
>>> bottom layer with a lot of copper. That's about like connecting
>>> with five thermal breaks, 50 mil wide and 62 mil long.
>>> 
>>> He wants to put them in the pad tenting them on the bottom to
>>> minimize wicking. I've never heard of that. Is that a thing? I've
>>> always heard that vias simply should not be in the pad, rather
>>> ring the pad with lots of copper. Then you can get a significant
>>> number of them, adequate to connect the bottom layer to the top
>>> thermally.
>>> 
>>> How do you do it?
>> That depends on the datasheet recommendations and/or our own
>> judgement. But we do use vias in pads for better thermal connection
>> to a plane if that is required. I don't know what you mean by
>> 'tenting', but we do use soldermask over those vias (and all
>> others) on the back of the board. Is that what you mean? Never had
>> problems with this. Another option is via plugging, but thats extra
>> board cost and I have no experience with it.
> 
> I've always had a hard time getting PCB fab houses to not clip my
> silkscreen around vias and pads.  The problem is they use much larger
> clipping regions than would seem to be required.  The assembly house
> was the middle man, but kept talking about how bad tented vias are,
> referring to closing off the via opening by the silkscreen or solder
> mask, potentially causing damage to the boards somehow.  They seemed
> to think it could cause bubbles in the solder mask or something.  I
> did get them to clip a lot smaller but they still clipped.

Yes, tenting can be problematic.  There are many factors involved - the
sizes of the holes, the type of solder, the type of soldering process,
the quality of the pcb production, the skill of the assemblers, the type
of assembly.

Vias in pads are fine if they are plated and plugged.  I believe we have
used that on some boards.  (I know we have also used some tented vias in
pads on older boards, and I know those were problematic but possible to
manufacture.)

You really need a good dialogue with the assembly house here, and /they/
need a good dialogue with the pcb manufacturer.

The best choice is always a balance - can you afford the greater cost
for plating and filling?  Can you afford the extra board space to have
the vias outside the pads?  Can you afford the reliability risk of
imperfectly produced boards?


> 
> If you tent the back side and cover the front side with solder paste
> and a chip, where does the air go that is trapped in the via when the
> board is reflowed raising the temperature so much?  At 250°C the
> pressure in the via is going to rise to 2 atm.  I expect if it
> doesn't do anything to the board it would tend to push the chip up
> and burp.  But then it depends on the number of size of the vias.
> Lots of smaller vias have less volume than fewer large ones.

Yes, that's the kind of problems you can expect.  Tents can be blown,
and you lose solder out the via.  And if they burp (I don't know if that
is a technical term, but I know what you mean) then you could get
short-circuits under the chip.  It's easy to end up with something that
works during board testing but has long-term reliability problems, and
repair of this kind of failure is going to be close to impossible as the
thermal connection makes rework impractical.  If you are going to try
tenting, you'll want to xray at least a few of the boards to see the
results.

> 
> The chip data sheet does not show any vias under the pads.  They show
> large areas of copper radiating from the chip.   VNH5019A
> 
> Any idea how much plating is found on vias on a board with the
> typical 1 oz copper?  I assume that start with 1/2 oz and plate up to
> 1 oz, so adding 1/2 oz.  Does that equate to 1/2 oz copper in the
> vias or somewhat less due to diffusion limitations?
> 

On Thursday, December 17, 2020 at 3:56:07 AM UTC-5, Stef wrote:
> On 2020-12-17 Rick C wrote in comp.arch.embedded: 
> > On Wednesday, December 16, 2020 at 6:50:06 PM UTC-5, Stef wrote: 
> >> On 2020-12-16 Rick C wrote in comp.arch.embedded: 
> >> > I'm helping with a board design of a few surface mount components with large thermal loads. The main problem is a part that has large pads. The guy is laying it out ignoring the suggestions of the data sheet and simply put five 16 mil drill vias to the bottom layer with a lot of copper. That's about like connecting with five thermal breaks, 50 mil wide and 62 mil long. 
> >> > 
> >> > He wants to put them in the pad tenting them on the bottom to minimize wicking. I've never heard of that. Is that a thing? I've always heard that vias simply should not be in the pad, rather ring the pad with lots of copper. Then you can get a significant number of them, adequate to connect the bottom layer to the top thermally. 
> >> > 
> >> > How do you do it? 
> >> That depends on the datasheet recommendations and/or our own judgement. But 
> >> we do use vias in pads for better thermal connection to a plane if that is 
> >> required. I don't know what you mean by 'tenting', but we do use soldermask 
> >> over those vias (and all others) on the back of the board. Is that what you 
> >> mean? Never had problems with this. Another option is via plugging, but 
> >> thats extra board cost and I have no experience with it. 
> > 
> > I've always had a hard time getting PCB fab houses to not clip my silkscreen around vias and pads. The problem is they use much larger clipping regions than would seem to be required. The assembly house was the middle man, but kept talking about how bad tented vias are, referring to closing off the via opening by the silkscreen or solder mask, potentially causing damage to the boards somehow. They seemed to think it could cause bubbles in the solder mask or something. I did get them to clip a lot smaller but they still clipped. 
> >
> Weird, never had that problem. Yes, they clip soldermask and silkscreen around 
> pads, but never around vias. Silkscreen over a via is usually a bit distorted, 
> but if you have no other space to put it, it's better than nothing. Our pcb 
> package has an option to use soldermask over vias or not. We always put 
> soldermask over the vias and if that is in the gerbers, that is wat we get on 
> the boards. Never tried what happens of we don't put soldermaks over the vias 
> but do have silkscreen over them.
> > If you tent the back side and cover the front side with solder paste and a chip, where does the air go that is trapped in the via when the board is reflowed raising the temperature so much? At 250°C the pressure in the via is going to rise to 2 atm. I expect if it doesn't do anything to the board it would tend to push the chip up and burp. But then it depends on the number of size of the vias. Lots of smaller vias have less volume than fewer large ones.
> The contribution of gasses from the solder paste itself is probably much 
> larger than that of the little bit of air in the vias. A paste grid 
> pattern can help to reduce problems with these gasses (voiding). 
> A page about that topic: https://fctsolder.com/solder-voiding/
> > The chip data sheet does not show any vias under the pads. They show large areas of copper radiating from the chip. VNH5019A
> The datasheet only shows some tested layouts and the thermal results. I 
> see no other recommendation than a "suggested pad layout". With these 
> pads and a little copper area on the side, you could place all the thermal 
> vias in the areas next to the pads and/or place them inside the pads. I 
> don't know what I would do in this case. Would also depend on the rest of 
> the layout. But I would use as much copper as possible on the top and then 
> decide where and how many thermal vias to use. A bit more compicated in 
> this case as the thermal pads are not in the same net. so you cannot just 
> connect all to a bottom ground plane.
> > Any idea how much plating is found on vias on a board with the typical 1 oz copper? I assume that start with 1/2 oz and plate up to 1 oz, so adding 1/2 oz. Does that equate to 1/2 oz copper in the vias or somewhat less due to diffusion limitations?
> I'm not so much in the oz thing. What I always hear is that the finished 
> hole size of a plated hole is 0.1mm smaller than the drill. So when I 
> design in a 0.3mm via, they use a 0.4mm drill and the expected plating 
> thickness inside the hole is 0.05mm.

That amounts to 2 mil copper which is more than 1oz (1.4 mil, 0.035mm).  Everything I've been told is they plate the full board when plating the vias, so that would add more than 1 oz to the rest of the board.  

I've always found it odd that there is so little real info on PCB layout and construction that you can hang your hat on.  The IPC standards are a good source, but I don't have access to them.  Otherwise I find many houses have info on their web sites that varies all over the map.  

The guy doing the layout may be responding to my concerns by himself expressing concerns.  In the meeting today we finally had a reasonable discussion and the board is going to be larger to have the full size pattern of 16^2 cm top side copper with the rest of the board laid around it.  

The three pads are the two motor connections and the input power connection.  The board is mounted in a fairly large enclosure with some natural airflow.  They may use a pair of small fans to keep the motor cool.  This board can't be located in that air stream unfortunately.  

Since we are not maxing out the capability of the chip I think we will be ok with 16 cm^2 done right.  It took a 2x4 up side his head to get the board guy's attention.  He also won't  change the connector for the motor switches.  We said weeks ago to make it a 10 pin ribbon cable, cheap and easy.  But he has on the board a 6 pin Molex connector with two parts and separate pins rather than buying a damn assembled ribbon cable for $1.50.   Buy a length twice what you need and cut it in half to make two cables.  Isn't that obviously the easy and simple path?  Why screw with crimp connectors? 

-- 

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

On 2020-12-18 Rick C wrote in comp.arch.embedded:
> On Thursday, December 17, 2020 at 3:56:07 AM UTC-5, Stef wrote:
>> On 2020-12-17 Rick C wrote in comp.arch.embedded: 

>> > Any idea how much plating is found on vias on a board with the typical 1 oz copper? I assume that start with 1/2 oz and plate up to 1 oz, so adding 1/2 oz. Does that equate to 1/2 oz copper in the vias or somewhat less due to diffusion limitations?
>> I'm not so much in the oz thing. What I always hear is that the finished 
>> hole size of a plated hole is 0.1mm smaller than the drill. So when I 
>> design in a 0.3mm via, they use a 0.4mm drill and the expected plating 
>> thickness inside the hole is 0.05mm.
>
> That amounts to 2 mil copper which is more than 1oz (1.4 mil, 0.035mm).  Everything I've been told is they plate the full board when plating the vias, so that would add more than 1 oz to the rest of the board.  

Well there could be some rounding here where 0.035 ~= 0.05. And yes,
through vias are plated with the complete board. Blind and burried vias
are plated in intermediate steps.

>
> I've always found it odd that there is so little real info on PCB layout and construction that you can hang your hat on.  The IPC standards are a good source, but I don't have access to them.  Otherwise I find many houses have info on their web sites that varies all over the map.  
>

Yes, each PCB house publishes there own rules and guidelines. But the
differences should not be that big (inside the same board classes)


> Since we are not maxing out the capability of the chip I think we will be ok with 16 cm^2 done right.  It took a 2x4 up side his head to get the board guy's attention.  He also won't  change the connector for the motor switches.  We said weeks ago to make it a 10 pin ribbon cable, cheap and easy.  But he has on the board a 6 pin Molex connector with two parts and separate pins rather than buying a damn assembled ribbon cable for $1.50.   Buy a length twice what you need and cut it in half to make two cables.  Isn't that obviously the easy and simple path?  Why screw with crimp connectors? 
>

Crimp connectors are usually fine for mass production, ask your cable
assembly house for the optimal choices for your particular layout and
quantities.

For low quantity self assembled protos using a ribbon cable may be easiest,
but ribbon cables have their drawbacks too. Without knowing the full
design, layout, cable routing etc., a 'best' solution cannot be chosen.

 
-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Majorities, of course, start with minorities.
		-- Robert Moses