Delta-sigma ADC question

I read in sci.electronics.design that Randy Yates 
<randy.yates@sonyericsson.com> wrote (in 
<xxpy8bo9l2n.fsf@usrts005.corpusers.net>) about 'Delta-sigma ADC 
question', on Tue, 12 Apr 2005:
>Ville Voipio <vvoipio@kosh.hut.fi> writes:
>> sigma delta sigma delta sigma delta [...]
>
>It's "delta sigma".

Both terms are used. I once thought they were different configurations, 
but it appears not. OTOH, the digma-selta converter has a higher alcohol 
content.
-- 
Regards, John Woodgate, OOO - Own Opinions Only.
There are two sides to every question, except
'What is a Moebius strip?'
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

Additionally, you might have to deal with delays. Typical delay times 
between analog input and digital output of delta-sigma ADs are around 15 
samples! This might make synching mux timing and sampled data hard to do.

Best regards,

Andre

Ville Voipio wrote:

> In article <xxpfyxwb6cn.fsf@usrts005.corpusers.net>, Randy Yates wrote:
> 
> 
>>Maybe you can enlighten me a bit here. Back in my old school/analog
>>days, I was taught that settling time is inversely proportional to
>>bandwidth. If I have a Fn Hz channel (from sampling at 2*Fn samples
>>per second), then why wouldn't the settling time of an input be the
>>same whether I used delta sigma or flash converter techniques?
> 
> 
> If the bandwidth is the same, then there is no difference between
> the converters.
> 
> But if you take a typical SAR converter, its analog bandwidth
> (before the sampling stage) is typically much larger than the
> sampling rate. For example, the AD7476 (1 Ms/s, 12-bit SAR ADC)
> has 1 Ms/s  maximum sampling rate and 6.5 MHz full-power (3 dB)
> bandwidth. This bandwidth will give LSB settling at the maximum 
> sampling rate.
> 
> On the other hand, the (pseudo-analog) bandwidth of a sigma-delta
> is almost exactly Fs/2. This means in this case there is 1:10
> ratio between the bandwidths, and this makes the difference in
> settling time.
> 
> - Ville
> 


-- 

Please change no_spam to a.lodwig when replying via email!

Randy Yates wrote:
> Mark Borgerson <mborgerson@comcast.net> writes:
>> marcsok@yahoo.com says...
>>>
>>> I am looking for an ADC 16+ bit resolution that would sample 64
>>> chanels at the rate of 25 Khz each. switching is planned to be
>>> done with a mux.
>>>
>>> I have heard that the sigma delta ADCs are not appropriate for
>>> this task
>>>
>>> Questions are:
>>>
>>> 1. If indeed they are'nt ,can some one explain why?
>>> 2. if not can any one point a specific SD ADC that can stand
>>>     they rates mentioned.
>>
>> Delta sigma converters  generally require several times as long
>> to get a stable output when switching inputs with a multiplexer
>> because the internal digital filters require settling time.
>>
>> You are looking at collecting 64 x 25000 samples per second or
>> 1.6MSamples per second. Multiply that times 3 for the extra
>> settling time, and you're going to need a REALLY fast clock for
>> the converter, and a very fast multiplexer.
>>
>> 64 channels times 25KHz is a problem better suited to multiple
>> faster converters.  The RADAR, SONAR, and ultrasound folks
>> might have a solution, but it won't be cheap!
> 
> Maybe you can enlighten me a bit here. Back in my old
> school/analog days, I was taught that settling time is inversely
> proportional to bandwidth. If I have a Fn Hz channel (from
> sampling at 2*Fn samples per second), then why wouldn't the
> settling time of an input be the same whether I used delta sigma
> or flash converter techniques?
> 
> I've heard this flavor of argument for years (decades?) against
> using delta sigma converters in multi-channel systems. It must
> be true - the folks who have used them would know (I have not).
> But as I've just queried, there's something that doesn't seem
> to add up, in my view.

Please don't toppost.  Your answer belongs after, or intermixed
with, the material you quote, with immaterial matter snipped out.

First, consider what a delta demodulator is:

  1 bit signal ----1 bit register-----integrator----->out analog
                       ^
  clock ---------------|

simple, huh?  Now, how do you make a delta encoder?

   clock-------------------------------------+
                                             |
   input signal--->-|----------+             v
                    |comparator|---->-1 bit register-+->out bits
               +-->-|----------+                     |
               |                                     |
               +---<-----the same demodulator-<------+

still simple, huh.  The demodulator is the integrator.  All that
has been added is a single comparator and feedback.  The integrator
is an op-amp with one resistor and one capacitor.  Any failure to
match time constants shows up as a gain factor. 

What it encodes is simple - is the input higher or lower than the
output at any given (clocked) moment.  The integrator has to
operate peacefully throughout the clock period, so there is nothing
to multiplex, except possibly the digital transmission path.

That is also why delta systems always have an output at 1/2 the
clock frequency.  They are never stable at a voltage level.

Contrast that with a flash, or almost any conventional ADC.  It
takes a sample, possibly holds it, and generates a multi-bit
representation of that sample.  The delta system generates a one
bit comparison, at a higher clock rate.

-- 
"If you want to post a followup via groups.google.com, don't use
 the broken "Reply" link at the bottom of the article.  Click on 
 "show options" at the top of the article, then click on the 
 "Reply" at the bottom of the article headers." - Keith Thompson

In article <xxpy8bo9l2n.fsf@usrts005.corpusers.net>, Randy Yates wrote:
> 
> It's "delta sigma".

Analog uses "sigma delta", Linear uses "delta sigma", TI/BB
uses "delta sigma". Maxim does not know which one to use:

  http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870

IIRC, Linear tried to make a big difference between delta-sigma
and sigma-delta when LTC2400 came around. There is indeed
a theoretical difference between the two topologies, but
as the difference is rather insignificant from the user's
point of view, the two terms seem to be used as synonyms.

Actually, it would be more precise to talk about "oversampling"
converters, because that's what makes the difference. Not the
actual converter topology or modulator order.

- Ville

-- 
Ville Voipio, Dr.Tech., M.Sc. (EE)

Ville Voipio wrote:
> 
> Actually, it would be more precise to talk about "oversampling"
> converters, because that's what makes the difference. Not the
> actual converter topology or modulator order.
> 
> - Ville
> 

Not exactly.  The pole in the feedback loop of a delta-sigma converter 
serves to take the nominally white quantization noise power and blue 
shift it into the higher frequencies, which if your mixed signal system 
is designed correctly will then be out of band from your signal, such 
that the quantization noise can be filtered and decimated out.  This is 
in contrast to just taking say an SAR, oversampling by N, filtering, and 
decimating, which doesn't perform this noise shaping because it doesn't 
have the feedback.

CBFalconer wrote:
> ...   The delta system generates a one
> bit comparison, at a higher clock rate.


Then that gets low-pass filtered, smoothing the choppy result and adding 
precision -- extra bits -- by averaging. The filter adds delay and needs 
to be flushed and refilled whenever the MUX selects a new input.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

OK.

--RY

CBFalconer <cbfalconer@yahoo.com> writes:

> Please don't toppost.  
- 
Randy Yates
Sony Ericsson Mobile Communications
Research Triangle Park, NC, USA
randy.yates@sonyericsson.com, 919-472-1124

Randy Yates wrote:
> Hi Mark,
> 
> Maybe you can enlighten me a bit here. Back in my old school/analog
> days, I was taught that settling time is inversely proportional to
> bandwidth. If I have a Fn Hz channel (from sampling at 2*Fn samples
> per second), then why wouldn't the settling time of an input be the
> same whether I used delta sigma or flash converter techniques?
> 
> I've heard this flavor of argument for years (decades?) against
> using delta sigma converters in multi-channel systems. It must
> be true - the folks who have used them would know (I have not). But
> as I've just queried, there's something that doesn't seem to add up,
> in my view. 

  The data sheets will usually show the settling time, and there ARE
SD chips, designed for MUX drive. (I think Linear offer some?)
  As is typical in design, it is a trade off....
-jg

On Tue, 12 Apr 2005 10:33:59 -0500, Rob Gaddi
<rgaddi@bcm.YUMMYSPAMtmc.edu> wrote:

>Ville Voipio wrote:
>> 
>> Actually, it would be more precise to talk about "oversampling"
>> converters, because that's what makes the difference. Not the
>> actual converter topology or modulator order.
>> 
>> - Ville
>> 
>
>Not exactly.  The pole in the feedback loop of a delta-sigma converter 
>serves to take the nominally white quantization noise power and blue 
>shift it into the higher frequencies, which if your mixed signal system 
>is designed correctly will then be out of band from your signal, such 
>that the quantization noise can be filtered and decimated out.  This is 
>in contrast to just taking say an SAR, oversampling by N, filtering, and 
>decimating, which doesn't perform this noise shaping because it doesn't 
>have the feedback.


I've never understood that. You'll have to explain it to me some day.

John

In article <xxpfyxwb6cn.fsf@usrts005.corpusers.net>, 
randy.yates@sonyericsson.com says...
> Hi Mark,
> 
> Maybe you can enlighten me a bit here. Back in my old school/analog
> days, I was taught that settling time is inversely proportional to
> bandwidth. If I have a Fn Hz channel (from sampling at 2*Fn samples
> per second), then why wouldn't the settling time of an input be the
> same whether I used delta sigma or flash converter techniques?
> 

The simple explanation seems to be that there are internal digital
filters that have to settle before the output is valid.  The number
and kind of internal filters determines the response to a step
input on the signal.

I'm sure someone else has (or will) explain in greater detail. If
not,  look into the data sheet on the CS5534 (a sigma-delta
converter with multiplexe inputs).
> I've heard this flavor of argument for years (decades?) against
> using delta sigma converters in multi-channel systems. It must
> be true - the folks who have used them would know (I have not). But
> as I've just queried, there's something that doesn't seem to add up,
> in my view. 
> 

If it was easy,  no one would pay us the big bucks for solving these
problems!   ;-)


<SNIP>

Mark Borgerson