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FIFO as a Logic Analyzer; Clock synthesizer

Started by Unknown April 21, 2005
Hi!
I have a big FIFO chip covered by dust, that I'd like to finally use.
The most useful application I'm imagining for it is to finally make
myself a logic analyzer. This FIFO (Texas Instruments SN74V3690-6PEU)
is a 3.3V device, but has 5V tolerant inputs. "Great!" I thought.

What I'm asking you is: should I connect the probes (just a header
cable) directly to the FIFO, or should I use an high speed buffer
inbetween? Consider that the chip is specced at 166MHz.

Moreover, what is the cheapest way to produce a variable clock
speed up to 166MHz (and possibly beyond, for other applications)?
A PLL? Any chip you may suggest me?

Thanks!
TPM

nospam@nospam.com wrote:

> Hi! > I have a big FIFO chip covered by dust, that I'd like to finally use. > The most useful application I'm imagining for it is to finally make > myself a logic analyzer. This FIFO (Texas Instruments SN74V3690-6PEU) > is a 3.3V device, but has 5V tolerant inputs. "Great!" I thought. > > What I'm asking you is: should I connect the probes (just a header > cable) directly to the FIFO, or should I use an high speed buffer > inbetween? Consider that the chip is specced at 166MHz. > > Moreover, what is the cheapest way to produce a variable clock > speed up to 166MHz (and possibly beyond, for other applications)? > A PLL? Any chip you may suggest me? > > Thanks! > TPM >
Why not a CPLD or FPGA. And do your own frequency synthesizer using an accumulator. For high speed accumulator, use pipeline methodology. Laurent www.amontec.com
On Thursday, in article
     <T5O9e.1269909$35.46767150@news4.tin.it> nospam@nospam.com
     wrote:

>Hi! >I have a big FIFO chip covered by dust, that I'd like to finally use. >The most useful application I'm imagining for it is to finally make >myself a logic analyzer. This FIFO (Texas Instruments SN74V3690-6PEU) >is a 3.3V device, but has 5V tolerant inputs. "Great!" I thought. > >What I'm asking you is: should I connect the probes (just a header >cable) directly to the FIFO, or should I use an high speed buffer >inbetween? Consider that the chip is specced at 166MHz.
I personally would buffer as a mistake on the inputs could blow the inexpensive buffer, and depends on how easy it is to get those FIFO chips in 6 months time.
>Moreover, what is the cheapest way to produce a variable clock >speed up to 166MHz (and possibly beyond, for other applications)? >A PLL? Any chip you may suggest me?
For quite a lot of PLLs I use ICS <http://www.icst.com/> whole range of fixed and programmeable PLL and clock drivers. Simple chip and an oscillator/crystal can get very cheap multiples, I find cheap and easy for video and LCD driving (lots of different clock rates). To achieve 166MHz will be something in their standard parts as quite a few parts have used that type of clock multiplied up from a much lowere clock.
>Thanks! >TPM
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